AT32UC3A4128S Atmel Corporation, AT32UC3A4128S Datasheet - Page 457
AT32UC3A4128S
Manufacturer Part Number
AT32UC3A4128S
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A4128S
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
AES
Sram (kbytes)
128
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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- AT32UC3A0128 PDF datasheet
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- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
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22.9.1
Name:
Access Type:
Offset:
Reset Value:
• TENBIT: Ten Bit Address Match
• ADR: Slave Address
• SOAM: Stretch Clock on Address Match
• CUP: NBYTES Count Up
• ACK: Slave Receiver Data Phase ACK Value
• PECEN: Packet Error Checking Enable
• SMHH: SMBus Host Header
• SMDA: SMBus Default Address
• SMBALERT: SMBus Alert
• SWRST: Software Reset
32072G–11/2011
SWRST
31
23
15
7
-
0: Disables Ten Bit Address Match.
1: Enables Ten Bit Address Match.
Slave address used in slave address match. Bits 9:0 are used if in 10-bit mode, bits 6:0 otherwise.
0: Does not stretch bus clock after address match.
1: Stretches bus clock after address match.
0: Causes NBYTES to count down (decrement) per byte transferred.
1: Causes NBYTES to count up (increment) per byte transferred.
0: Causes a low value to be returned in the ACK cycle of the data phase in slave receiver mode.
1: Causes a high value to be returned in the ACK cycle of the data phase in slave receiver mode.
0: Disables SMBus PEC (CRC) generation and check.
1: Enables SMBus PEC (CRC) generation and check.
0: Causes the TWIS not to acknowledge the SMBus Host Header.
1: Causes the TWIS to acknowledge the SMBus Host Header.
0: Causes the TWIS not to acknowledge the SMBus Default Address.
1: Causes the TWIS to acknowledge the SMBus Default Address.
0: Causes the TWIS to release the SMBALERT line and not to acknowledge the SMBus Alert Response Address (ARA).
1: Causes the TWIS to pull down the SMBALERT line and to acknowledge the SMBus Alert Response Address (ARA).
This bit will always read as 0.
Writing a zero to this bit has no effect.
Control Register
SOAM
30
22
14
6
-
-
CR
Read/Write
0x00
0x00000000
CUP
29
21
13
5
-
-
STREN
ACK
28
20
12
4
-
ADR[7:0]
GCMATCH
PECEN
27
19
11
3
-
SMATCH
TENBIT
SMHH
26
18
10
2
SMDA
SMEN
25
17
9
1
ADR[9:8]
SMBALERT
SEN
24
16
8
0
457
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