AT32UC3A4128S Atmel Corporation, AT32UC3A4128S Datasheet - Page 327

• Manufacturer Part Number: AT32UC3A4128S
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A4128S

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: AES
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

19.9.1.4
19.9.2
32072G–11/2011
Ending Multi-block Transfers
Suspension of Transfers Between Blocks
blocks is a function of CTLx.LLP_S_EN, CFGx.RELOAD_SR, CTLx.LLP_D_EN, and
CFGx.RELOAD_DS registers (see
Note:
At the end of every block transfer, an end of block interrupt is asserted if:
Note:
For rows 6, 8, and 10 of
transfers. For example, at the end of block N, the DMACA automatically proceeds to block N + 1.
For rows 2, 3, 4, 7, and 9 of
block transfers), the DMA transfer automatically stalls after the end of block. Interrupt is asserted
if the end of block interrupt is enabled and unmasked.
The DMACA does not proceed to the next block transfer until a write to the block interrupt clear
register, ClearBlock[n], is performed by software. This clears the channel block complete
interrupt.
For rows 2, 3, 4, 7, and 9 of
block transfers), the DMA transfer does not stall if either:
Channel suspension between blocks is used to ensure that the end of block ISR (interrupt ser-
vice routine) of the next-to-last block is serviced before the start of the final block commences.
This ensures that the ISR has cleared the CFGx.RELOAD_SR and/or CFGx.RELOAD_DS bits
before comp letion of the fina l block. Th e reload bits CFGx.RELOAD_SR and/or
CFGx.RELOAD_DS should be cleared in the ‘end of block ISR’ for the next-to-last block
transfer.
All multi-block transfers must end as shown in either Row 1 or Row 5 of
At the end of every block transfer, the DMACA samples the row number, and if the DMACA is in
Row 1 or Row 5 state, then the previous block transferred was the last block and the DMA trans-
fer is terminated.
Note:
For rows 2,3 and 4 of
C F G x . R E L O A D _ D S i s s e t ) , m u l t i - b l o c k D M A t r a n s f e r s c o n t i n u e u n t i l b o t h t h e
CFGx.RELOAD_SR and CFGx.RELOAD_DS registers are cleared by software. They should be
• interrupts are enabled, CTLx.INT_EN = 1
• the channel block interrupt is unmasked, MaskBlock[n] = 0, where n is the channel number.
• interrupts are disabled, CTLx.INT_EN = 0, or
• the channel block interrupt is masked, MaskBlock[n] = 1, where n is the channel number.
Both SARx and DARx updates cannot be selected to be contiguous. If this functionality is
required, the size of the Block Transfer (CTLx.BLOCK_TS) must be increased. If this is at the
maximum value, use Row 10 of
block descriptor to be equal to the end SARx address of the previous block. Similarly, setup the
LLI.DARx address of the block descriptor to be equal to the end DARx address of the previous
block.
The block complete interrupt is generated at the completion of the block transfer to the
destination.
Row 1 and Row 5 are used for single block transfers or terminating multiblock transfers. Ending in
Row 5 state enables status fetch for the last block. Ending in Row 1 state disables status fetch for
the last block.
Table 19-1 on page
Table 19-1 on page
Table 19-1 on page 326
Table 19-1 on page 326
Figure 19-1 on page
Table 19-1 on page 326
326, the DMA transfer does not stall between block
326, (LLPx = 0 and CFGx.RELOAD_SR and/or
(SARx and/or DARx auto-reloaded between
(SARx and/or DARx auto-reloaded between
316).
and setup the LLI.SARx address of the
Table 19-1 on page
326.
327