AT32UC3A4128S Atmel Corporation, AT32UC3A4128S Datasheet - Page 52

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AT32UC3A4128S

Manufacturer Part Number
AT32UC3A4128S
Description
Manufacturer
Atmel Corporation

Specifications of AT32UC3A4128S

Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
AES
Sram (kbytes)
128
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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32072G–11/2011
Figure 7-6.
In addition to the listed reset types, the JTAG can keep parts of the device statically reset
through the JTAG Reset Register. See JTAG documentation for details.
Table 7-3.
When a reset occurs, some parts of the chip are not necessarily reset, depending on the reset
source. Only the Power On Reset (POR) will force a reset of the whole chip.
R E S E T _ N
Reset source
Power-on Reset
External Reset
Brownout Reset
CPU Error
Watchdog Timer
OCD
P o w e r-O n
B ro w n o u t
D e te c to r
D e te c to r
J T A G
W D T
O C D
Reset Controller Block Diagram
Reset Description
Description
Supply voltage below the power-on reset detector
threshold voltage
RESET_N pin asserted
Supply voltage below the brownout reset detector
threshold voltage
Caused by an illegal CPU access to external memory
while in Supervisor mode
See watchdog timer documentation.
See On-Chip Debug documentation
R C _ R C A U S E
C o n tro lle r
R e s e t
O C D , R T C /W D T ,
C lo c k G e n e ra to r
C P U , H S B ,
P B A , P B B
52

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