AT32UC3A4128S Atmel Corporation, AT32UC3A4128S Datasheet - Page 200

• Manufacturer Part Number: AT32UC3A4128S
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A4128S

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: AES
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Figure 15-24. TDF Optimization Disabled (MODE.TDFMODE = 0). TDF Wait States between Read and Write accesses on
15.6.7
15.6.7.1
15.6.7.2
32072G–11/2011
Write2 controlling
Read1 controlling
NBS0, NBS1,
signal(NWE)
signal(NRD)
A[AD_MSB:2]
CLK_SMC
A0, A1
D[15:0]
External Wait
Restriction
Frozen mode
the Same Chip Select.
Any access can be extended by an external device using the NWAIT input signal of the SMC.
The External Wait Mode field of the MODE register (MODE.EXNWMODE) on the corresponding
chip select must be written to either two (frozen mode) or three (ready mode). When the
MODE.EXNWMODE field is written to zero (disabled), the NWAIT signal is simply ignored on
the corresponding chip select. The NWAIT signal delays the read or write operation in regards to
the read or write controlling signal, depending on the read and write modes of the corresponding
chip select.
When one of the MODE.EXNWMODE is enabled, it is mandatory to program at least one hold
cycle for the read/write controlling signal. For that reason, the NWAIT signal cannot be used in
Page Mode
The NWAIT signal is assumed to be a response of the external device to the read/write request
of the SMC. Then NWAIT is examined by the SMC only in the pulse state of the read or write
controlling signal. The assertion of the NWAIT signal outside the expected period has no impact
on SMC behavior.
When the external device asserts the NWAIT signal (active low), and after internal synchroniza-
tion of this signal, the SMC state is frozen, i.e., SMC internal counters are frozen, and all control
signals remain unchanged. When the synchronized NWAIT signal is deasserted, the SMC com-
pletes the access, resuming the access from the point where it was stopped. See
on page
delay the access and to freeze the SMC.
TDFCYCLES = 5
Read1 cycle
201. This mode must be selected when the external device uses the NWAIT signal to
(Section
Read1 hold = 1
15.6.9), or in Slow Clock Mode
Read to Write
Wait State
TDFCYCLES = 5
4 TDF WAIT STATES
(Section
15.6.8).
Write2 setup = 1
(optimization disabled)
TDFMODE=0
Write 2 cycle
Figure 15-25
200