AT32UC3A4128S Atmel Corporation, AT32UC3A4128S Datasheet - Page 726

• Manufacturer Part Number: AT32UC3A4128S
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A4128S

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: AES
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

• NBUSYBK: Number of Busy Banks
• DTSEQ: Data Toggle Sequence
• SHORTPACKETI: Short Packet Interrupt
• RXSTALLDI: Received STALLed Interrupt
• CRCERRI: CRC Error Interrupt
• OVERFI: Overflow Interrupt
• NAKEDI: NAKed Interrupt
32072G–11/2011
This field may be updated 1 clock cycle after the RWALL bit changes, so the user shall not poll this field as an interrupt bit.
This field indicates the number of busy bank.
For OUT pipe, this field indicates the number of busy bank(s), filled by the user, ready for OUT transfer. When all banks are
busy, this triggers an PnINT interrupt if UPCONn.NBUSYBKE is one.
For IN pipe, this field indicates the number of busy bank(s) filled by IN transaction from the Device. When all banks are free, this
triggers an PnINT interrupt if UPCONn.NBUSYBKE is one.
This field indicates the data PID of the current bank.
For OUT pipe, this field indicates the data toggle of the next packet that will be sent.
For IN pipe, this field indicates the data toggle of the received packet stored in the current bank.
This bit is set when a short packet is received by the host controller (packet length inferior to the PSIZE programmed field).
This bit is cleared when the SHORTPACKETIC bit is written to one.
This bit is set, for all endpoints but isochronous, when a STALL handshake has been received on the current bank of the pipe.
The Pipe is automatically frozen. This triggers an interrupt if the RXSTALLE bit is one.
This bit is cleared when the RXSTALLDIC bit is written to one.
This bit is set, for isochronous endpoint, when a CRC error occurs on the current bank of the Pipe. This triggers an interrupt if
the TXSTPE bit is one.
This bit is cleared when the CRCERRIC bit is written to one.
This bit is set when the current pipe has received more data than the maximum length of the current pipe. An interrupt is
triggered if the OVERFIE bit is one.
This bit is cleared when the OVERFIC bit is written to one.
This bit is set when a NAK has been received on the current bank of the pipe. This triggers an interrupt if the NAKEDE bit is one.
0
1
1
0
0
1
1
0
0
1
1
NBUSYBK
CURRBK
DTSEQ
1
0
1
0
1
0
1
0
1
0
1
Current Bank
Bank1
Bank2 if supported
Reserved
Number of busy bank
All banks are free.
1 busy bank
2 busy banks if supported
reserved
Data toggle sequence
Data0
Data1
reserved
reserved
(see
Table 26-1 on page
(see
Table 26-1 on page
617).
617).
726