AT32UC3A4128S Atmel Corporation, AT32UC3A4128S Datasheet - Page 490

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AT32UC3A4128S

Manufacturer Part Number
AT32UC3A4128S
Description
Manufacturer
Atmel Corporation

Specifications of AT32UC3A4128S

Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
AES
Sram (kbytes)
128
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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23.9.1
Name:
Access Type:
Offset:
Reset Value:
• STOP: Stop the Current Transfer
• SWRST: Software Reset
• SMDIS: SMBus Disable
• SMEN: SMBus Enable
• MDIS: Master Disable
• MEN: Master Enable
32072G–11/2011
SWRST
31
23
15
7
-
-
-
Writing a one to this bit terminates the current transfer, sending a STOP condition after the shifter has become idle. If there are
additional pending transfers, they will have to be explicitly restarted by software after the STOP condition has been successfully
sent.
Writing a zero to this bit has no effect.
If the TWIM master interface is enabled, writing a one to this bit resets the TWIM. All transfers are halted immediately, possibly
violating the bus semantics.
If the TWIM master interface is not enabled, it must first be enabled before writing a one to this bit.
Writing a zero to this bit has no effect.
Writing a one to this bit disables SMBus mode.
Writing a zero to this bit has no effect.
Writing a one to this bit enables SMBus mode.
Writing a zero to this bit has no effect.
Writing a one to this bit disables the master interface.
Writing a zero to this bit has no effect.
Writing a one to this bit enables the master interface.
Writing a zero to this bit has no effect.
Control Register
30
22
14
6
-
-
-
-
CR
Write-only
0x00
0x00000000
SMDIS
29
21
13
5
-
-
-
SMEN
28
20
12
4
-
-
-
27
19
11
3
-
-
-
-
26
18
10
2
-
-
-
-
MDIS
25
17
9
1
-
-
-
STOP
MEN
24
16
8
0
-
-
490

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