AT32UC3A4128S Atmel Corporation, AT32UC3A4128S Datasheet - Page 694

• Manufacturer Part Number: AT32UC3A4128S
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A4128S

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: AES
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

• CURRBK: Current Bank
• NBUSYBK: Number of Busy Banks
• ERRORTRANS: High-bandwidth isochronous OUT endpoint transaction error Interrupt
• DTSEQ: Data Toggle Sequence
32072G–11/2011
This bit is set for non-control endpoints, to indicate the current bank:
This field may be updated one clock cycle after the RWALL bit changes, so the user should not poll this field as an interrupt bit.
This field is set to indicate the number of busy banks:
For IN endpoints, it indicates the number of banks filled by the user and ready for IN transfer. When all banks are free, this
triggers an EPnINT interrupt if NBUSYBKE is one.
For OUT endpoints, it indicates the number of banks filled by OUT transactions from the host. When all banks are busy, this
triggers an EPnINT interrupt if NBUSYBKE is one.
When the FIFOCON bit is cleared (by writing a one to the FIFOCONC bit) to validate a new bank, this field is updated two or
three clock cycles later to calculate the address of the next bank.
An EPnINT interrupt is triggered if:
- for IN endpoint, NBUSYBKE is one and all the banks are free.
- for OUT endpoint, NBUSYBKE is one and all the banks are busy.
This bit is set when a transaction error occurs during the current micro-frame (the data toggle sequencing does not respect the
usb 2.0 standard). This triggers an EPnINT interrupt if ERRORTRANSE is one.
This bit is set as long as the current bank (CURRBK) belongs to the bad n-transactions (n=1,2 or 3) transferred during the
micro-frame. Shall be cleared by software by clearing (at least once) the FIFOCON bit to switch to the bank that belongs to the
next n-transactions (next micro-frame).
Look at the UFEATURES register to know if the high-bandwidth isochronous feature is supported by the device.
This field is set to indicate the PID of the current bank:
For IN transfers, it indicates the data toggle sequence that will be used for the next packet to be sent. This is not relative to the
current bank.
0
0
1
1
0
0
1
1
0
0
1
1
NBUSYBK
CURRBK
DTSEQ
0
1
0
1
0
1
0
1
0
1
0
1
Current Bank
Bank0
Bank1
Bank2 if supported
Reserved
Number of Busy Banks
0 (all banks free)
1
2
3 if supported
Data Toggle Sequence
Data0
Data1
Data2 (for high-bandwidth isochronous endpoint)
MData (for high-bandwidth isochronous endpoint)
(see
(see
Table 26-1 on page
Table 26-1 on page
617).
617).
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