AT32UC3L0128 Atmel Corporation, AT32UC3L0128 Datasheet - Page 220
AT32UC3L0128
Manufacturer Part Number
AT32UC3L0128
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3L0128.pdf
(85 pages)
4.AT32UC3L0128.pdf
(852 pages)
Specifications of AT32UC3L0128
Flash (kbytes)
128 Kbytes
Pin Count
48
Max. Operating Frequency
50 MHz
Cpu
32-bit AVR
# Of Touch Channels
17
Hardware Qtouch Acquisition
Yes
Max I/o Pins
36
Ext Interrupts
36
Usb Speed
No
Usb Interface
No
Spi
5
Twi (i2c)
2
Uart
4
Lin
4
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
460
Analog Comparators
8
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.62 to 3.6
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
35
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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13.6.10
Name:
Access Type:
Reset Value:
• COARSE: Coarse Calibration Value
• FINE: FINE Calibration Value
• QLEN: Quick Lock Enable
• CCEN: Chill Cycle Enable
• LLAW: Lose Lock After Wake
• DITHER: Enable Dithering
• MODE: Mode Selection
• EN: Enable
Note that this register is protected by a lock. To write to this register the UNLOCK register has to be written first. Please
refer to the UNLOCK register description for details.
32145A–12/2011
31
23
15
7
-
-
Set the value of the coarse calibration register. If in closed loop mode, this field is Read-only.
Set the value of the fine calibration register. If in closed loop mode, this field is Read-only.
0: Quick Lock is disabled.
1: Quick Lock is enabled.
0: Chill Cycle is disabled.
1: Chill Cycle is enabled.
0: Locks will not be lost after waking up from sleep modes.
1: Locks will be lost after waking up from sleep modes where the DFLL clock has been stopped.
0: The fine LSB input to the VCO is constant.
1: The fine LSB input to the VCO is dithered to achieve sub-LSB approximation to the correct multiplication ratio.
0: The DFLL is in open loop operation.
1: The DFLL is in closed loop operation.
0: The DFLL is disabled.
1: The DFLL is enabled.
DFLLn Configuration Register
QLEN
30
22
14
DFLLnCONF
Read/Write
0x00000000
6
-
CCEN
29
21
13
5
-
28
20
12
4
-
-
COARSE[7:0]
FINE[7:0]
LLAW
27
19
11
3
-
DITHER
26
18
10
2
-
AT32UC3L0128/256
MODE
25
17
9
1
-
FINE[8]
EN
24
16
8
0
220
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