AT32UC3L0128 Atmel Corporation, AT32UC3L0128 Datasheet - Page 299

• Manufacturer Part Number: AT32UC3L0128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3L0128

• Flash (kbytes): 128 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

15.5.3
15.5.4
15.5.5
32145A–12/2011
Disabling the WDT
Flash Calibration
Special Considerations
The WDT is disabled by writing a zero to the CTRL.EN bit. When disabling the WDT no other
bits in the CTRL Register should be changed until the CTRL.EN bit reads back as zero. If the
CTRL.CEN bit is written to zero, the CTRL.EN bit will never read back as zero if changing the
value from one to zero.
The WDT can be enabled at reset. This is controlled by the WDTAUTO fuse. The WDT will be
set in basic mode, RCSYS is set as source for CLK_CNT, and PSEL will be set to a value giving
T
how to program the fuses.
If the Flash Calibration Done (FCD) bit in the CTRL Register is zero at a watchdog reset the
flash calibration will be redone, and the CTRL.FCD bit will be set when the calibration is done. If
CTRL.FCD is one at a watchdog reset, the configuration of the WDT will not be changed during
flash calibration. After any other reset the flash calibration will always be done, and the
CTRL.FCD bit will be set when the calibration is done.
Care must be taken when selecting the PSEL/TBAN values so that the timeout period is greater
than the startup time of the device. Otherwise a watchdog reset will reset the device before any
code has been run. This can also be avoided by writing the CTRL.DAR bit to one when configur-
ing the WDT.
If the Store Final Value (SFV) bit in the CTRL Register is one, the CTRL Register is locked for
further write accesses. All writes to the CTRL Register will be ignored. Once the CTRL Register
is locked, it can only be unlocked by a reset (e.g. POR, OCD, and WDT).
The CTRL.MODE bit can only be changed when the WDT is disabled (CTRL.EN=0).
psel
above 100 ms. Please refer to the Fuse Settings chapter for details about WDTAUTO and
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