AT32UC3L0128 Atmel Corporation, AT32UC3L0128 Datasheet - Page 206

• Manufacturer Part Number: AT32UC3L0128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3L0128

• Flash (kbytes): 128 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32145A–12/2011
The interrupt sources will generate an interrupt request if the corresponding bit in the Interrupt
Mask Register is set. The interrupt sources are ORed together to form one interrupt request. The
SCIF will generate an interrupt request if at least one of the bits in the Interrupt Mask Register
(IMR) is set. Bits in IMR are set by writing a one to the corresponding bit in the Interrupt Enable
Register (IER), and cleared by writing a one to the corresponding bit in the Interrupt Disable
Register (IDR). The interrupt request remains active until the corresponding bit in the Interrupt
Status Register (ISR) is cleared by writing a one to the corresponding bit in the Interrupt Clear
Register (ICR). Because all the interrupt sources are ORed together, the interrupt request from
the SCIF will remain active until all the bits in ISR are cleared.
• PLLLOCK - PLL Lock
• PLLLOCKLOST - PLL Lock Lost
• BRIFARDY - Backup Register Interface Ready.
• DFLL0RCS - DFLL Reference Clock Stopped:
• DFLL0RDY - DFLL Ready:
• DFLL0LOCKLOSTA - DFLL lock lost on Accurate value:
• DFLL0LOCKLOSTF - DFLL lock lost on Fine value:
• DFLL0LOCKLOSTC - DFLL lock lost on Coarse value:
• DFLL0LOCKA - DFLL Locked on Accurate value:
• DFLL0LOCKF - DFLL Locked on Fine value:
• DFLL0LOCKC - DFLL Locked on Coarse value:
• BODDET - Brown out detection:
• SM33DET - Supply Monitor 3.3V Detector:
• VREGOK - Voltage Regulator OK:
• OSC0RDY - Oscillator Ready:
• OSC32RDY - 32KHz Oscillator Ready:
– A 0 to 1 transition on the PCLKSR.PLLLOCK bit is detected.
– A to 1 transition on the PCLKSR.PLLLOCKLOST bit is detected.
– A 0 to 1 transition on the PCLKSR.BRIFARDY bit is detected.
– A 0 to 1 transition on the PCLKSR.DFLLRCS bit is detected.
– A 0 to 1 transition on the PCLKSR.DFLLRDY bit is detected.
– A 0 to 1 transition on the PCLKSR.DFLLLOCKLOSTA bit is detected.
– A 0 to 1 transition on the PCLKSR.DFLLLOCKLOSTF bit is detected.
– A 0 to 1 transition on the PCLKSR.DFLLLOCKLOSTC bit is detected.
– A 0 to 1 transition on the PCLKSR.DFLLLOCKA bit is detected.
– A 0 to 1 transition on the PCLKSR.DFLLLOCKF bit is detected.
– A 0 to 1 transition on the PCLKSR.DFLLLOCKC bit is detected.
– A 0 to 1 transition on the PCLKSR.BODDET bit is detected.
– A 0 to 1 transition on the PCLKSR.SM33DET bit is detected.
– A 0 to 1 transition on the PCLKSR.VREGOK bit is detected.
– A 0 to 1 transition on the PCLKSR.OSC0RDY bit is detected.
– A 0 to 1 transition on the PCLKSR.OSC32RDY bit is detected.
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