AT32UC3L0128 Atmel Corporation, AT32UC3L0128 Datasheet - Page 391
AT32UC3L0128
Manufacturer Part Number
AT32UC3L0128
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3L0128.pdf
(85 pages)
4.AT32UC3L0128.pdf
(852 pages)
Specifications of AT32UC3L0128
Flash (kbytes)
128 Kbytes
Pin Count
48
Max. Operating Frequency
50 MHz
Cpu
32-bit AVR
# Of Touch Channels
17
Hardware Qtouch Acquisition
Yes
Max I/o Pins
36
Ext Interrupts
36
Usb Speed
No
Usb Interface
No
Spi
5
Twi (i2c)
2
Uart
4
Lin
4
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
460
Analog Comparators
8
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.62 to 3.6
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
35
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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Figure 19-20. SPI Transfer Format (CPHA=0, 8 bits per transfer)
19.6.4.4
19.6.4.5
19.6.4.6
19.6.5
32145A–12/2011
SPI Master -> RXD
CLK cycle (for reference)
SPI Master -> TXD
SPI Master -> RTS
SPI Slave -> RXD
SPI Slave -> TXD
SPI Slave -> CTS
(CPOL= 0)
(CPOL= 1)
LIN Mode
MOSI
MISO
CLK
NSS
CLK
Receiver and Transmitter Control
Character Transmission and Reception
Receiver Time-out
See
In SPI master mode, the slave select line (NSS) is asserted low one bit period before the start of
transmission, and released high one bit period after every character transmission. A delay for at
least three bit periods is always inserted in between characters. In order to address slave
devices supporting the Chip Select Active After Transfer (CSAAT) mode, NSS can be forced low
by writing a one to the Force SPI Chip Select bit (CR.RTSEN/FCS). Releasing NSS when FCS
is one, is only possible by writing a one to the Release SPI Chip Select bit (CR.RTSDIS/RCS).
In SPI slave mode, a low level on NSS for at least one bit period will allow the slave to initiate a
transmission or reception. The Underrun Error bit (CSR.UNRE) is set if a character must be sent
while THR is empty, and TXD will be high during character transmission, as if 0xFF was being
sent. If a new character is written to THR it will be sent correctly during the next transmission
slot. Writing a one to CR.RSTSTA will clear UNRE. To ensure correct behavior of the receiver in
SPI slave mode, the master device sending the frame must ensure a minimum delay of one bit
period in between each character transmission.
Receiver Time-out’s are not possible in SPI mode as the baud rate clock is only active during
data transfers.
The USART features a LIN (Local Interconnect Network) 1.3 and 2.0 compliant mode, embed-
ding full error checking and reporting, automatic frame processing with up to 256 data bytes,
”Transmitter Operations” on page
1
MSB
MSB
2
6
6
3
5
5
4
382, and
4
4
5
”Receiver Operations” on page
3
3
6
AT32UC3L0128/256
2
2
7
1
1
8
LSB
LSB
384.
391
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