AT32UC3L0128 Atmel Corporation, AT32UC3L0128 Datasheet - Page 476

• Manufacturer Part Number: AT32UC3L0128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3L0128

• Flash (kbytes): 128 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Figure 21-7. Master Write with Multiple Data Bytes
21.8.4
32145A–12/2011
SR.IDLE
TXRDY
TWD
Master Receiver Mode
NBYTES set to n
S
Write THR
(DATAn)
DADR
TWI transfers require the slave to acknowledge each received data byte. During the acknowl-
edge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull
it down in order to generate the acknowledge. The master polls the data line during this clock
pulse and sets the Data Acknowledge bit (DNACK) in the Status Register if the slave does not
acknowledge the data byte. As with the other status bits, an interrupt can be generated if
enabled in the Interrupt Enable Register (IER).
TXRDY is used as Transmit Ready for the Peripheral DMA Controller transmit channel.
The end of a command is marked when the TWIM sets the SR.CCOMP bit. See
Figure
Figure 21-6. Master Write with One Data Byte
A START condition is transmitted and master receiver mode is initiated when the bus is free and
CMDR has been written with START=1 and READ=1. START and SADR+R will then be trans-
mitted. During the address acknowledge clock pulse (9th pulse), the master releases the data
line (HIGH), enabling the slave to pull it down in order to acknowledge the address. The master
polls the data line during this clock pulse and sets the Address Not Acknowledged bit (ANAK) in
the Status Register if no slave acknowledges the address.
After the address phase, the following is repeated:
while (NBYTES>0)
SR.IDLE
TXRDY
W
TWD
21-7.
A
Write THR (DATA)
NBYTES set to 1
S
(DATAn+1)
Write THR
DATAn
DADR
A
W
A
DATAn+5
Last data sent
(DATAn+m)
Write THR
DATA
(ACK received and NBYTES=0)
A
AT32UC3L0128/256
STOP sent automatically
A
DATAn+m
P
(ACK received and NBYTES=0)
STOP sent automatically
A
P
Figure 21-6
and
476