AT32UC3L0128 Atmel Corporation, AT32UC3L0128 Datasheet - Page 821
AT32UC3L0128
Manufacturer Part Number
AT32UC3L0128
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3L0128.pdf
(85 pages)
4.AT32UC3L0128.pdf
(852 pages)
Specifications of AT32UC3L0128
Flash (kbytes)
128 Kbytes
Pin Count
48
Max. Operating Frequency
50 MHz
Cpu
32-bit AVR
# Of Touch Channels
17
Hardware Qtouch Acquisition
Yes
Max I/o Pins
36
Ext Interrupts
36
Usb Speed
No
Usb Interface
No
Spi
5
Twi (i2c)
2
Uart
4
Lin
4
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
460
Analog Comparators
8
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.62 to 3.6
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
35
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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Table 32-43. SPI Timing, Slave Mode
Note:
32.9.5
32145A–12/2011
Symbol
SPI6
SPI7
SPI8
SPI9
SPI10
SPI11
SPI12
SPI13
SPI14
SPI15
1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
TWIM/TWIS Timing
cess technology. These values are not covered by test limits in production.
Parameter
SPCK falling to MISO delay
MOSI setup time before SPCK rises
MOSI hold time after SPCK rises
SPCK rising to MISO delay
MOSI setup time before SPCK falls
MOSI hold time after SPCK falls
NPCS setup time before SPCK rises
NPCS hold time after SPCK falls
NPCS setup time before SPCK falls
NPCS hold time after SPCK rises
Maximum SPI Frequency, Slave Input Mode
The maximum SPI slave input frequency is given by the following formula:
Where
CPOL and NCPHA.
ter for a description of this clock.
Maximum SPI Frequency, Slave Output Mode
The maximum SPI slave output frequency is given by the following formula:
Where
SPI master setup time. Please refer to the SPI master datasheet for
imum frequency of the SPI pins. Please refer to the I/O Pin Characteristics section for the
maximum frequency of the pins.
Figure 32-44
them. Some of these requirements (t
vention. Compliance with the other requirements (t
TWI
, t
HIGH
SPIn
SPIn
, and f
(1)
shows the TWI-bus timing requirements and the compliance of the device with
is the MISO delay, SPI6 or SPI9 depending on CPOL and NCPHA.
is the MOSI setup and hold time, SPI7 + SPI8 or SPI10 + SPI11 depending on
TWCK
) requires user intervention through appropriate programming of the relevant
f
CLKSPI
f
SPCKMAX
is the maximum frequency of the CLK_SPI. Refer to the SPI chap-
f
SPCKMAX
3.0V to 3.6V,
Conditions
V
capacitor =
maximum
r
=
VDDIO
external
and t
40pF
MIN f
=
from
f
) are met by the device without requiring user inter-
(
MIN f
PINMAX
(
HD-STA
CLKSPI
,
------------------------------------
SPIn
, t
,
Min
SU-STA
----------- -
SPIn
AT32UC3L0128/256
6.0
5.5
3.4
1.1
3.3
0.7
0
0
+
1
1
t
SETUP
)
, t
SU-STO
)
t
SETUP
, t
HD-DAT
.
Max
29.4
29.0
f
PINMAX
, t
SU-DAT-TWI
t
SETUP
is the max-
Units
ns
, t
is the
LOW-
821
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