ATmega32M1 Atmel Corporation, ATmega32M1 Datasheet - Page 118

• Manufacturer Part Number: ATmega32M1
• Manufacturer: Atmel Corporation

Specifications of ATmega32M1

• Flash (kbytes): 32 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 27
• Ext Interrupts: 27
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 1
• Can: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 14
• Input Capture Channels: 1
• Pwm Channels: 10
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

118
ATmega16M1/32M1/64M1
to 0x0003), and the maximum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM reso-
lution in bits can be calculated by using the following equation:
In phase correct PWM mode the counter is incremented until the counter value matches either
one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGMn3:0 = 1, 2, or 3), the value in ICRn
(WGMn3:0 = 10), or the value in OCRnA (WGMn3:0 = 11). The counter has then reached the
TOP and changes the count direction. The TCNTn value will be equal to TOP for one timer clock
cycle. The timing diagram for the phase correct PWM mode is shown on
shows phase correct PWM mode when OCRnA or ICRn is used to define TOP. The TCNTn
value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The
diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on
the TCNTn slopes represent compare matches between OCRnx and TCNTn. The OCnx Inter-
rupt Flag will be set when a compare match occurs.
Figure 15-8. Phase Correct PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches BOTTOM. When
either OCRnA or ICRn is used for defining the TOP value, the OCnA or ICFn Flag is set accord-
ingly at the same timer clock cycle as the OCRnx Registers are updated with the double buffer
value (at TOP). The Interrupt Flags can be used to generate an interrupt each time the counter
reaches the TOP or BOTTOM value.
When changing the TOP value the program must ensure that the new TOP value is higher or
equal to the value of all of the Compare Registers. If the TOP value is lower than any of the
Compare Registers, a compare match will never occur between the TCNTn and the OCRnx.
Note that when using fixed TOP values, the unused bits are masked to zero when any of the
OCRnx Registers are written. As the third period shown in
TOP actively while the Timer/Counter is running in the phase correct mode can result in an
unsymmetrical output. The reason for this can be found in the time of update of the OCRnx Reg-
ister. Since the OCRnx update occurs at TOP, the PWM period starts and ends at TOP. This
TCNTn
OCnx
OCnx
Period
1
R
PCPWM
2
=
log
---------------------------------- -
(
log
TOP
3
2 ( )
+
1
Figure 15-8
)
4
illustrates, changing the
Figure
OCRnx/TOP Update and
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
TOVn Interrupt Flag Set
(Interrupt on Bottom)
15-8. The figure
8209D–AVR–11/10
(COMnx1:0 = 2)
(COMnx1:0 = 3)