ATmega32M1 Atmel Corporation, ATmega32M1 Datasheet - Page 60

• Manufacturer Part Number: ATmega32M1
• Manufacturer: Atmel Corporation

Specifications of ATmega32M1

• Flash (kbytes): 32 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 27
• Ext Interrupts: 27
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 1
• Can: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 14
• Input Capture Channels: 1
• Pwm Channels: 10
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

12.2
12.2.1
12.2.2
60
Register Description
ATmega16M1/32M1/64M1
EICRA – External Interrupt Control Register A
EIMSK – External Interrupt Mask Register
The External Interrupt Control Register A contains control bits for interrupt sense control.
• Bit 7:0 – ISC3[1:0] - ISC0[1:0]: Interrupt Sense Control 3 to 0, Bit 1 and Bit 0
The External Interrupts 3, 2, 1 and 0 are activated by the external pins INT3:0 if the SREG I-flag
and the corresponding interrupt mask in the EIMSK is set. The level and edges on the external
pins that activate the interrupt are defined in
chronously. The value on the INT3:0 pins are sampled before detecting edges. If edge or toggle
interrupt is selected, pulses that last longer than one clock period will generate an interrupt.
Shorter pulses are not guaranteed to generate an interrupt. Observe that CPU clock frequency
can be lower than XTAL frequency if the XTAL divider is enabled. If low level interrupt is
selected, the low level must be held until the completion of the currently executing instruction to
generate an interrupt. If enabled, a level triggered interrupt will generate an interrupt request as
long as the pin is held low.
Table 12-1.
Note:
• Bit 7:4 – Res: Reserved
These bits are reserved and will always read as zero.
• Bit 3:0 – INT[3:0]: External Interrupt Request 3:0 Enable
When an INT3:0 bit is written to one and the I-bit in the Status Register (SREG) is set (one), the
corresponding external pin interrupt is enabled. The Interrupt Sense Control bits in the External
Interrupt Control Register A - EICRA defines whether the external interrupt is activated on rising
or falling edge or level sensed. Activity on any of these pins will trigger an interrupt request even
if the pin is enabled as an output. This provides a way of generating a software interrupt.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
ISCn1
0
0
1
1
1. n = 3, 2, 1 or 0.
When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt
Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed.
ISCn0
Interrupt Sense Control
ISC31
0
1
0
1
R/W
7
0
R
7
–
0
Description
The low level of INTn generates an interrupt request.
Any logical change on INTn generates an interrupt request.
The falling edge between two samples of INTn generates an interrupt request.
The rising edge between two samples of INTn generates an interrupt request.
ISC30
R/W
6
0
R
6
–
0
ISC21
R/W
5
0
R
5
–
0
(1)
ISC20
R/W
4
0
R
4
–
0
Table
ISC11
12-1. Edges on INT3:0 are registered asyn-
R/W
INT3
3
0
R
3
0
ISC10
R/W
INT2
2
0
R
2
0
ISC01
R/W
INT1
R/W
1
0
1
0
ISC00
R/W
INT0
R/W
0
0
0
0
8209D–AVR–11/10
EICRA
EIMSK