ATmega32M1 Atmel Corporation, ATmega32M1 Datasheet - Page 182
ATmega32M1
Manufacturer Part Number
ATmega32M1
Description
Manufacturer
Atmel Corporation
Specifications of ATmega32M1
Flash (kbytes)
32 Kbytes
Pin Count
32
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
27
Ext Interrupts
27
Usb Speed
No
Usb Interface
No
Spi
1
Uart
1
Can
1
Lin
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
125
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
14
Input Capture Channels
1
Pwm Channels
10
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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Manufacturer
Quantity
Price
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19.10.2
182
ATmega16M1/32M1/64M1
CANGSTA – CAN General Status Register
• Bit 0 – SWRES: Software Reset Request
This auto resettable bit only resets the CAN controller.
• Bit 7 – Res: Reserved
This bit is reserved and will always read as zero.
• Bit 6 – OVRG: Overload Frame Flag
This flag does not generate an interrupt.
• Bit 5 – Res: Reserved
This bit is reserved and will always read as zero.
• Bit 4 – TXBSY: Transmitter Busy
This flag does not generate an interrupt.
• Bit 3 – RXBSY: Receiver Busy
This flag does not generate an interrupt.
Initial Value
Read/Write
– 0 - standby mode: The on-going transmission (if exists) is normally terminated and the
– 1 - enable mode: The CAN channel enters in enable mode once 11 recessive bits
– 0 - no reset
– 1 - reset: this reset is “ORed” with the hardware reset
– 0 - no overload frame
– 1 - overload frame: set by hardware as long as the produced overload frame is sent
– 0 - transmitter not busy
– 1 - transmitter busy: set by hardware as long as a frame (data, remote, overload or
– 0 - receiver not busy
– 1 - receiver busy: set by hardware as long as a frame is received or monitored
Bit
CAN channel is frozen (the CONMOB bits of every MOb do not change). The transmitter
constantly provides a recessive level. In this mode, the receiver is not enabled but all the
registers and mailbox remain accessible from CPU. In this mode, the receiver is not
enabled but all the registers and mailbox remain accessible from CPU
has been read
error frame) or an ACK field is sent. Also set when an inter frame space is sent
Note:A standby mode applied during a reception may corrupt the on-going reception or set the
controller in a wrong state. The controller will restart correctly from this state if a software
reset (SWRES) is applied. If no reset is considered, a possible solution is to wait for a lake of
a receiver busy (RXBSY) before to enter in stand-by mode. The best solution is first to apply
an abort request command (ABRQ) and then wait for the lake of the receiver busy (RXBSY)
before to enter in stand-by mode. In any cases, this standby mode behavior has no effect on
the CAN bus integrity
7
-
-
-
OVRG
R
6
0
5
-
-
-
TXBSY
R
4
0
RXBSY
R
3
0
ENFG
R
2
0
BOFF
R
1
0
ERRP
R
0
0
8209D–AVR–11/10
CANGSTA
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