ATmega32M1 Atmel Corporation, ATmega32M1 Datasheet - Page 242

• Manufacturer Part Number: ATmega32M1
• Manufacturer: Atmel Corporation

Specifications of ATmega32M1

• Flash (kbytes): 32 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 27
• Ext Interrupts: 27
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 1
• Can: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 14
• Input Capture Channels: 1
• Pwm Channels: 10
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

21.10 Register Description
21.10.1
242
ATmega16M1/32M1/64M1
ADMUX – ADC Multiplexer Register
The ADC of the ATmega16M1/32M1/64M1 is controlled through 3 different registers. The ADC-
SRA and the ADCSRB registers which are the ADC Control and Status registers, and the
ADMUX which allows to select the VREF source and the channel to be converted.
The configuration of the amplifiers are controlled via two dedicated registers AMP0CSR and
AMP1CSR. Then the start of conversion is done via the ADC control and status registers.
The conversion result is stored on ADCH and ADCL register which contain respectively the most
significant bits and the less significant bits.
Bit
Read/Write
Initial Value
• Bit 7:6 – REFS[1:0]: ADC Vref Selection Bits
These 2 bits determine the voltage reference for the ADC.
The different setting are shown in
Table 21-4.
If bits REFS1 and REFS0 are changed during a conversion, the change will not take effect until
this conversion is complete (it means while the ADIF bit in ADCSRA register is set).
In case the internal Vref is selected, it is turned ON as soon as an analog feature needed it is
set.
• Bit 5 – ADLAR: ADC Left Adjust Result
Set this bit to left adjust the ADC result.
Clear it to right adjust the ADC result.
The ADLAR bit affects the configuration of the ADC result data registers. Changing this bit
affects the ADC data registers immediately regardless of any on going conversion. For a com-
plete description of this bit, see
AREFEN
1
1
0
1
1
0
ISRCEN
ADC Voltage Reference Selection
REFS1
0
0
0
0
0
x
R/W
7
0
REFS0
REFS[1:0]
R/W
6
0
00
01
01
10
11
11
“ADCH and ADCL – ADC Result Data Registers” on page
ADLAR
Table
R/W
5
0
Description
External Vref on AREF pin, Internal Vref is switched off
AVcc with external capacitor connected on the AREF pin
AVcc (no external capacitor connected on the AREF pin)
Reserved
Internal 2.56V Reference voltage with external capacitor
connected on the AREF pin
Internal 2.56V Reference voltage
21-4.
MUX4
4
0
-
MUX3
R/W
3
0
MUX2
R/W
2
0
MUX1
R/W
1
0
MUX0
R/W
0
0
8209D–AVR–11/10
ADMUX
245.