ATmega32M1 Atmel Corporation, ATmega32M1 Datasheet - Page 206

• Manufacturer Part Number: ATmega32M1
• Manufacturer: Atmel Corporation

Specifications of ATmega32M1

• Flash (kbytes): 32 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 27
• Ext Interrupts: 27
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 1
• Can: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 14
• Input Capture Channels: 1
• Pwm Channels: 10
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

20.5
20.5.1
20.5.2
20.5.3
20.5.4
206
LIN / UART Description
ATmega16M1/32M1/64M1
Reset
Clock
LIN Protocol Selection
Configuration
The AVR core reset logic signal also resets the LIN/UART controller. Another form of reset
exists, a software reset controlled by LSWRES bit in LINCR register. This self-reset bit performs
a partial reset as shown in
Table 20-2.
The I/O clock signal (clk
LIN13 bit in LINCR register is used to select the LIN protocol:
The controller checks the LIN13 bit in computing the checksum (enhanced checksum in LIN2.1 /
classic checksum in LIN 1.3). See
This bit is irrelevant for UART commands.
Depending on the mode (LIN or UART), LCONF[1..0] bits of the LINCR register set the controller
in the following configuration
Table 20-3.
• LIN13 = 0 (default): LIN 2.1 protocol
• LIN13 = 1: LIN 1.3 protocol
Mode
LIN
LIN Status & Interrupt Reg.
LIN Enable Interrupt Reg.
LIN Baud Rate Reg. High
LIN Data Buffer Selection
LIN Baud Rate Reg. Low
LIN Data Length Reg.
LIN Bit Timing Reg.
LIN Identifier Reg.
LIN Control Reg.
LIN Error Reg.
Register
LCONF[1..0]
LIN Data
Reset of LIN/UART Registers
Configuration Table versus Mode
00
01
10
11
b
b
b
b
i/o
) also clocks the LIN/UART controller. It is its unique clock.
Table
(Table
LINBRRH
LINBRRL
LINENIR
20-2.
LINERR
LINBTR
LINDLR
LINSEL
LINDAT
LINSIR
LINIDR
LINCR
Name
“Rx & TX Response Functions” on page
20-3):
No CRC field detection or transmission
LIN standard configuration (default)
Reset Value
0000 0000
0000 0000
0000 0000
0000 0000
0010 0000
0000 0000
0000 0000
0000 0000
1000 0000
0000 0000
0000 0000
Frame_Time_Out disable
Listening mode
Configuration
b
b
b
b
b
b
b
b
b
b
b
LSWRES Value
0000 0000
0000 0000
0000 0000
0010 0000
uuuu uuuu
0000 0000
1000 0000
0000 0000
xxxx 0000
xxxx uuuu
xxxx 0000
b
b
b
b
b
b
b
b
b
b
b
204.
u=unchanged
8209D–AVR–11/10
x=unknown
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