ATmega32M1 Atmel Corporation, ATmega32M1 Datasheet - Page 69
ATmega32M1
Manufacturer Part Number
ATmega32M1
Description
Manufacturer
Atmel Corporation
Specifications of ATmega32M1
Flash (kbytes)
32 Kbytes
Pin Count
32
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
27
Ext Interrupts
27
Usb Speed
No
Usb Interface
No
Spi
1
Uart
1
Can
1
Lin
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
125
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
14
Input Capture Channels
1
Pwm Channels
10
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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Quantity
Price
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13.3
8209D–AVR–11/10
Alternate Port Functions
Most port pins have alternate functions in addition to being general digital I/Os.
shows how the port pin control signals from the simplified
ridden by alternate functions. The overriding signals may not be present in all port pins, but the
figure serves as a generic description applicable to all port pins in the AVR microcontroller
family.
Figure 13-5. Alternate Port Functions
Note:
Table 13-2 on page 70
indexes from
generated internally in the modules having the alternate function.
Pxn
1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk
DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE
DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE
DDOExn: Pxn DATA DIRECTION OVERRIDE ENABLE
PUOExn: Pxn PULL-UP OVERRIDE ENABLE
PUOVxn: Pxn PULL-UP OVERRIDE VALUE
DDOVxn: Pxn DATA DIRECTION OVERRIDE VALUE
PVOExn: Pxn PORT VALUE OVERRIDE ENABLE
PVOVxn: Pxn PORT VALUE OVERRIDE VALUE
PTOExn: Pxn, PORT TOGGLE OVERRIDE ENABLE
SLEEP: SLEEP CONTROL
SLEEP, and PUD are common to all ports. All other signals are unique for each pin
Figure 13-5
summarizes the function of the overriding signals. The pin and port
are not shown in the succeeding tables. The overriding signals are
1
0
1
0
1
0
1
0
PUOExn
PUOVxn
DIEOExn
DDOExn
DDOVxn
PVOExn
PVOVxn
DIEOVxn
SLEEP
(1)
SYNCHRONIZER
ATmega16M1/32M1/64M1
D
L
SET
CLR
Q
Q
AIOxn: ANALOG INPUT/OUTPUT PIN n ON PORTx
WDx: WRITE DDRx
WRx: WRITE PORTx
PUD: PULLUP DISABLE
WPx: WRITE PINx
clk
DIxn: DIGITAL INPUT PIN n ON PORTx
RDx: READ DDRx
RRx: READ PORTx REGISTER
RPx: READ PORTx PIN
D
PINxn
I/O
CLR
: I/O CLOCK
Q
Q
Figure 13-2 on page 65
RESET
RESET
PORTxn
Q
Q
Q
Q
DDxn
CLR
CLR
D
D
1
0
clk
PUD
WDx
RRx
DIxn
AIOxn
RDx
RPx
I/O
WRx
PTOExn
WPx
can be over-
Figure 13-5
I/O
,
69
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