ATmega32M1 Atmel Corporation, ATmega32M1 Datasheet - Page 136
ATmega32M1
Manufacturer Part Number
ATmega32M1
Description
Manufacturer
Atmel Corporation
Specifications of ATmega32M1
Flash (kbytes)
32 Kbytes
Pin Count
32
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
27
Ext Interrupts
27
Usb Speed
No
Usb Interface
No
Spi
1
Uart
1
Can
1
Lin
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
125
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
14
Input Capture Channels
1
Pwm Channels
10
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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Company
Part Number
Manufacturer
Quantity
Price
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Part Number:
ATmega32M1-15AD
Manufacturer:
ATMEL
Quantity:
1 448
Part Number:
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Manufacturer:
ATMEL/爱特梅尔
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Company:
Part Number:
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Manufacturer:
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Quantity:
210
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17.5.3
17.5.3.1
136
ATmega16M1/32M1/64M1
Operation Mode Descriptions
One Ramp Mode (Edge-Aligned)
Figure 17-3. Cycle Presentation in Centered Mode
Figure 17-2 on page 135
ter. Centered Mode is like One Ramp Mode which counts down and then up.
Notice that the update of the waveform generator registers is done regardless of ramp Mode at
the end of the PSC cycle.
Waveforms and duration of output signals are determined by parameters held in the registers
(POCRnSA, POCRnRA, POCRnSB, POCR_RB) and by the running mode. Two modes are
possible:
The following figure shows the resultant outputs PSCOUTnA and PSCOUTnB operating in one
ramp mode over a PSC cycle.
PSC Counter Value
• One Ramp Mode. In this mode, all the 3 PSCOUTnB outputs are edge-aligned and the 3
• Center Aligned Mode. In this mode, all the 6 PSC outputs are aligned at the center of the
PSCOUTnA can be also edge-aligned when setting the same values in the dedicated
registers.
In this mode, the PWM frequency is twice the Center Aligned Mode PWM frequency
period. Except when using the same duty cycles on the 3 modules, the edges of the outputs
are not aligned. So the PSC outputs do not commute at the same time, thus the system
which is driven by these outputs will generate less commutation noise.
In this mode, the PWM frequency is twice slower than in One Ramp Mode
and
Figure 17-3
graphically illustrate the values held in the PSC coun-
One PSC Cycle
8209D–AVR–11/10
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