ATmega32M1 Atmel Corporation, ATmega32M1 Datasheet - Page 152

• Manufacturer Part Number: ATmega32M1
• Manufacturer: Atmel Corporation

Specifications of ATmega32M1

• Flash (kbytes): 32 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 27
• Ext Interrupts: 27
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 1
• Can: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 14
• Input Capture Channels: 1
• Pwm Channels: 10
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

17.16.11 PIFR – PSC Interrupt Flag Register
152
ATmega16M1/32M1/64M1
• Bit 2 – PEVE1: PSC External Event 1 Interrupt Enable
When this bit is set, an external event which can generates a fault on module 1 generates also
an interrupt.
• Bit 1 – PEVE: PSC External Event 0 Interrupt Enable
When this bit is set, an external event which can generates a fault on module 0 generates also
an interrupt.
• Bit 0 – PEOPE: PSC End Of Cycle Interrupt Enable
When this bit is set, an interrupt is generated when PSC reaches the end of the whole cycle.
Bit
Read/Write
Initial Value
• Bit 7:4 – Res: Reserved
These bits are reserved and will always read as zero.
• Bit 3 – PEV2: PSC External Event 2 Interrupt
This bit is set by hardware when an external event which can generates a fault on module 2
occurs.
Must be cleared by software by writing a one to its location.
This bit can be read even if the corresponding interrupt is not enabled (PEVE2 bit = 0).
• Bit 2 – PEV1: PSC External Event 1 Interrupt
This bit is set by hardware when an external event which can generates a fault on module 1
occurs.
Must be cleared by software by writing a one to its location.
This bit can be read even if the corresponding interrupt is not enabled (PEVE1 bit = 0).
• Bit 1 – PEV: PSC External Event 0 Interrupt
This bit is set by hardware when an external event which can generates a fault on module 0
occurs.
Must be cleared by software by writing a one to its location.
This bit can be read even if the corresponding interrupt is not enabled (PEVE0 bit = 0).
• Bit 0 – PEOP: PSC End Of Cycle Interrupt
This bit is set by hardware when an “end of PSC cycle” occurs.
Must be cleared by software by writing a one to its location.
This bit can be read even if the corresponding interrupt is not enabled (PEOPE bit = 0).
R
7
0
-
R
6
0
-
R
5
0
-
R
4
0
-
PEV2
R/W
3
0
PEV1
R/W
2
0
PEV0
R/W
1
0
PEOP
R/W
0
0
8209D–AVR–11/10
PIFR