ATmega32M1 Atmel Corporation, ATmega32M1 Datasheet - Page 135

• Manufacturer Part Number: ATmega32M1
• Manufacturer: Atmel Corporation

Specifications of ATmega32M1

• Flash (kbytes): 32 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 27
• Ext Interrupts: 27
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 1
• Can: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 14
• Input Capture Channels: 1
• Pwm Channels: 10
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

17.5
17.5.1
17.5.2
8209D–AVR–11/10
Functional Description
Generation of Control Waveforms
Waveform Cycles
The PSC is based on the use of a free-running 12-bit counter (PSC counter). This counter is
able to count up to a top value determined by the contents of POCR_RB register and then
according to the selected running mode, count down or reset to zero for another cycle.
As can be seen from the block diagram
modules.
Each of the 3 PSC modules can be seen as two symetrical entities. One entity named part A
which generates the output PSCOUTnA and the second one named part B which generates the
PSCOUTnB output.
Each module has its own PSC Input circuitry which manages the corresponding input.
In general, the drive of a 3 phase motor requires the generation of 6 PWM signals. The duty
cycle of these signals must be independently controlled to adjust the speed or torque of the
motor or to produce the wanted waveform on the 3 voltage lines (trapezoidal, sinusoidal, and so
on).
In case of cross conduction or overtemperature, having inputs which can immediately disable
the waveform generator’s outputs is desirable.
These considerations are common for many systems which require PWM signals to drive power
systems such as lighting, DC/DC converters, and so on.
Each of the 3 modules has 2 waveform generators which jointly compose the output signal.
The first part of the waveform is relative to part A or PSCOUTnA output. This waveform corre-
sponds to sub-cycle A in the following figure.
The second part of the waveform is relative to part B or PSCOUTnB output. This waveform cor-
responds to sub-cycle B in the following figure.
The complete waveform is terminated at the end of the sub-cycle B, whereupon any changes to
the settings of the waveform generator registers will be implemented, for the next cycle.
The PSC can be configured in one of two modes (1Ramp Mode or Centered Mode). This config-
uration will affect the operation of all the waveform generators.
Figure 17-2. Cycle Presentation in One Ramp Mode
PSC Counter Value
Sub-Cycle A
One PSC Cycle
Sub-Cycle B
Figure 17-1 on page
ATmega16M1/32M1/64M1
UPDATE
134, the PSC is composed of 3
135