ATmega32M1 Atmel Corporation, ATmega32M1 Datasheet - Page 148

• Manufacturer Part Number: ATmega32M1
• Manufacturer: Atmel Corporation

Specifications of ATmega32M1

• Flash (kbytes): 32 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 27
• Ext Interrupts: 27
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 1
• Can: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 14
• Input Capture Channels: 1
• Pwm Channels: 10
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

17.16.3
17.16.4
17.16.5
148
ATmega16M1/32M1/64M1
POCRnSAH and POCRnSAL – PSC Output Compare SA Register
POCRnRAH and POCRnRAL – PSC Output Compare RA Register
POCRnSBH and POCRnSBL – PSCOutput Compare SB Register
• Bit 1:0 – PSYNC0[1:0]: Synchronization Out for ADC Selection
Select the polarity and signal source for generating a signal which will be sent from module 0 to
the ADC for synchronization.
Table 17-8.
Table 17-9.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
PSYNCn1
0
0
1
1
PSYNCn1
0
0
1
1
Synchronization Source Description in One Ramp Mode
Synchronization Source Description in Centered Mode
PSYNCn0
0
1
0
1
PSYNCn0
0
1
0
1
R/W
R/W
R/W
7
–
0
7
–
0
7
–
0
R/W
R/W
R/W
6
–
0
6
–
0
6
–
0
Description
Send signal on match with OCRnRA (during counting down of PSC). The
min value of OCRnRA must be 1
Send signal on match with OCRnRA (during counting up of PSC). The
min value of OCRnRA must be 1
no synchronization signal
no synchronization signal
Description
Send signal on leading edge of PSCOUTnA(match with OCRnSA)
Send signal on trailing edge of PSCOUTnA(match with OCRnRA or
fault/retrigger on part A)
Send signal on leading edge of PSCOUTnB (match with OCRnSB)
Send signal on trailing edge of PSCOUTnB (match with OCRnRB or
fault/retrigger on part B)
R/W
R/W
R/W
5
–
0
5
–
0
5
–
0
R/W
R/W
R/W
POCRnSA[7:0]
POCRnRA[7:0]
POCRnSB[7:0]
4
–
0
4
–
0
4
–
0
R/W
R/W
R/W
3
0
3
0
3
0
R/W
R/W
R/W
POCRnSA[11:8]
POCRnRA[11:8]
POCRnSB[11:8]
2
0
2
0
2
0
R/W
R/W
R/W
1
0
1
0
1
0
R/W
R/W
R/W
0
0
0
0
0
0
8209D–AVR–11/10
POCRnSAH
POCRnRAH
POCRnRAL
POCRnSBH
POCRnSAL
POCRnSBL