ATxmega32D4 Atmel Corporation, ATxmega32D4 Datasheet - Page 6
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ATxmega32D4
Manufacturer Part Number
ATxmega32D4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega32D4
Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
4
Twi (i2c)
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
14
Input Capture Channels
14
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega32D4-AU
Manufacturer:
Atmel
Quantity:
123
Part Number:
ATxmega32D4-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATxmega32D4-CU
Manufacturer:
Maxim
Quantity:
71
Company:
Part Number:
ATxmega32D4-MH
Manufacturer:
Atmel
Quantity:
1 910
Company:
Part Number:
ATxmega32D4-MH
Manufacturer:
Atmel
Quantity:
1 704
Part Number:
ATxmega32D4-MH
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
8210B–AVR–04/10
Figure 3-1.
The Arithmetic Logic Unit (ALU) supports arithmetic and logic operations between registers or
between a constant and a register. Single register operations can also be executed in the ALU.
After an arithmetic operation, the Status Register is updated to reflect information about the
result of the operation.
The ALU is directly connected to the fast-access Register File. The 32 x 8-bit general purpose
working registers all have single clock cycle access time allowing single-cycle Arithmetic Logic
Unit (ALU) operation between registers or between a register and an immediate. Six of the 32
registers can be used as three 16-bit address pointers for program and data space addressing -
enabling efficient address calculations.
The memory spaces are all linear and regular memory maps. The Data Memory space and the
Program Memory space are two different memory spaces.
The Data Memory space is divided into I/O registers and SRAM. In addition the EEPROM can
be memory mapped in the Data Memory.
All I/O status and control registers reside in the lowest 4K bytes addresses of the Data Memory.
This is referred to as the I/O Memory space. The lowest 64 addresses can be accessed directly,
or as the data space locations from 0x00 - 0x3F. The rest is the Extended I/O Memory space,
ranging from 0x40 to 0x1FFF. I/O registers here must be access as data space locations using
load (LD/LDS/LDD) and store (ST/STS/STD) instructions.
The SRAM holds data, and code cannot be executed from here. It can easily be accessed
through the five different addressing modes supported in the AVR architecture. The first SRAM
address is 0x2000.
Data address 0x1000 to 0x1FFF is reserved for memory mapping of EEPROM.
Peripheral
M odule 1
Block Diagram of the AVR Architecture
CONTROL
STATUS/
Program
Counter
OCD
Peripheral
M odule n
Instruction
Instruction
Program
Register
M em ory
Decode
Flash
DATA BUS
SRAM
DATA BUS
ALU
EEPROM
32 x 8 General
Registers
M ultiplier
Purpose
PM IC
XMEGA D
6