ATxmega32D4 Atmel Corporation, ATxmega32D4 Datasheet - Page 87

• Manufacturer Part Number: ATxmega32D4
• Manufacturer: Atmel Corporation

Specifications of ATxmega32D4

• Flash (kbytes): 32 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Speed: No
• Usb Interface: No
• Spi: 4
• Twi (i2c): 2
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 12
• Adc Speed (ksps): 200
• Analog Comparators: 2
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 14
• Input Capture Channels: 14
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

8.5
8.5.1
8.5.2
8210B–AVR–04/10
Register Description
STATUS - Reset Status Register
CTRL - Reset Control Register
• Bit 7:6 - Reserved
These bits are reserved and will always be read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bit 5 - SRF: Software Reset Flag
This flag is set if a Software reset occurs. The flag will be cleared by a power-on reset or by writ-
ing a one to the bit location.
• Bit 4 - PDIRF: Program and Debug Interface Reset Flag
This flag is set if a Programming interface reset occurs. The flag will be cleared by a power-on
reset or by writing a one to the bit location.
• Bit 3 - WDRF: Watchdog Reset Flag
This flag is set if a Watchdog reset occurs. The flag will be cleared by a power-on reset or by
writing a one to the bit location.
• Bit 2 - BORF: Brown Out Reset Flag
This flag is set if a Brown out reset occurs. The flag will be cleared by a power-on reset or by
writing a one to the bit location.
• Bit 1 - EXTRF: External Reset Flag
This flag is set if an External reset occurs. The flag will be cleared by a power-on reset or by writ-
ing a one to the bit location.
• Bit 0 - PORF: Power On Reset Flag
This flag is set if a Power-on reset occurs. Writing a one to the flag will clear the bit location.
• Bit 7:1 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
Bit
+0x01
Read/Write
Initial Value
Bit
+0x00
Read/Write
Initial Value
R
7
–
0
R
7
–
–
R
6
–
0
6
–
R
–
SRF
R/W
R
5
–
0
5
–
PDIRF
R/W
R
4
–
0
4
–
WDRF
R/W
R
3
–
0
3
–
BORF
R/W
R
2
–
0
2
–
EXTRF
R/W
1
–
R
0
1
–
XMEGA D
SWRST
PORF
R/W
R/W
0
0
0
–
STATUS
CTRL
87