MSC8101DS Motorola / Freescale Semiconductor, MSC8101DS Datasheet - Page 14

• Manufacturer Part Number: MSC8101DS
• Description: MSC8101 Network Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

1.4
The PowerPC System Bus, HDI16, and Interrupt signals are grouped together because they use a common set
of signal lines. Individual assignment of a signal to a specific signal line is configured through registers in the
System Interface Unit (SIU) and the Host Interface (HDI16). Table 1-5 describes the signals in this group.
Note:
Although there are eight interrupt request (IRQ) connections to the core processor, there are multiple external
lines that can connect to these internal signal lines. After reset, the default configuration includes two IRQ1
and two IRQ7 input lines. The designer must select one line for each required interrupt and reconfigure the
other external signal line or lines for alternate functions.
1-8
A[0–31]
TT[0–4]
TSIZ[0–3]
TBST
IRQ1
GBL
Signal
PowerPC System Bus, HDI16, and Interrupt Signals
To boot from the host interface, the HDI16 must be enabled by pulling up the HPE signal line
during PORESET. If the HPE signal is pulled up, the configuration word must then be loaded from
the host. The configuration word must set the Internal Space Port Size bit in the Bus Control
Register (BCR[ISPS]) to change the PowerPC system data bus width from 64 bits to 32 bits and
reassign the upper 32 bits to their HDI16 functions. Never set the Host Port Enable (HEN) bit in
the Host Port Control Register (HPCR) to enable the HDI16, unless the bus size is first changed
from 64 bits to 32 bits by setting the BCR[ISPS] bit. Otherwise, unpredictable operation may
occur.
Input/Output Address Bus
Input/Output Bus Transfer Type
Input/Output Transfer Size
Input/Output Bus Transfer Burst
Input/Output
Data Flow
Input
Table 1-5. PowerPC System Bus, HDI16, and Interrupt Signals
When the MSC8101 is in external master bus mode, these pins function as the address
bus. The MSC8101 drives the address of its internal bus masters and responds to
addresses generated by external bus masters. When the MSC8101 is in Internal Master
Bus mode, these pins are used as address lines connected to memory devices and are
controlled by the MSC8101 memory controller.
The bus master drives these pins during the address tenure to specify the type of
transaction.
The bus master drives these pins with a value indicating the number of bytes transferred
in the current transaction.
The bus master asserts this pin to indicate that the current transaction is a burst
transaction (transfers four quad words).
Interrupt Request 1
One of eight external lines that can request a service routine, via the internal interrupt
controller, from the SC140 core.
Global
When a master within the chip initiates a bus transaction, it drives this pin. When an
external master initiates a bus transaction, it should drive this pin. Assertion of this pin
indicates that the transfer is global and it should be snooped by caches in the system.
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MSC8101 Technical Data
1
Description