MSC8101DS Motorola / Freescale Semiconductor, MSC8101DS Datasheet - Page 27

• Manufacturer Part Number: MSC8101DS
• Description: MSC8101 Network Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

PA28
PA27
General-
Purpose
I/O
FCC1: RXENB
UTOPIA master
FCC1: RXENB
UTOPIA slave
FCC1: TX_EN
MII
FCC1: RXSOC
UTOPIA master
FCC1: RXSOC
UTOPIA slave
FCC1: RX_DV
MII
Peripheral Controller:
Name
Dedicated Signal
Protocol
Table 1-7. Port A Signals (Continued)
MSC8101 Technical Data
Dedicated
Direction
I/O Data
Output
Output
Output
Input
Input
Input
FCC1: UTOPIA Master Receive Enable
In the ATM UTOPIA interface supported by FCC1. (UTOPIA
master) RXENB is asserted by the MSC8101 (UTOPIA master
PHY) to indicate that RXD[0–7] and RXSOC are to be sampled
at the end of the next cycle. RXD[0–7] and RXSOC are
enabled only in cycles following those with RXENB asserted.
FCC1: UTOPIA Master Receive Enable
In the ATM UTOPIA interface supported by FCC1. (UTOPIA
slave) RXENB is an input asserted by an external PHY to
indicate that RXD[0–7] and RXSOC is to be sampled at the
end of the next cycle. RXD[0–7] and RXSOC are enabled only
in cycles following those with RXENB asserted.
FCC1: Media Independent Interface Transmit Enable
In the MII interface supported by FCC1. TX_EN is asserted by
the MSC8101 when transmitting data.
FCC1: UTOPIA Receive Start of Cell
Asserted by an external PHY when RXD[0–7] contains the first
valid byte of the cell.
FCC1: UTOPIA Receive Start of Cell
Asserted by the MSC8101 (UTOPIA slave) for an external
PHY when RXD[0–7] contains the first valid byte of the cell.
FCC1: Media Independent Interface Receive Data Valid
In the MII interface supported by FCC1. RX_DV is an input
asserted by an external fast Ethernet PHY. RX_DV indicates
that valid data is being sent. The presence of carrier sense but
not RX_DV indicates reception of broken packet headers,
probably due to bad wiring or a bad circuit.
Description
Port A Signals
1-21