MSC8101DS Motorola / Freescale Semiconductor, MSC8101DS Datasheet - Page 32

• Manufacturer Part Number: MSC8101DS
• Description: MSC8101 Network Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

1-26
Port A Signals
PA12
PA11
PA10
PA9
General-
Purpose
I/O
FCC1: RXD2
UTOPIA
SDMA: MSNUM3
FCC1: RXD1
UTOPIA
SDMA: MSNUM4
FCC1: RXD0
UTOPIA
SDMA: MSNUM5
SMC2: SMTXD
SI1 TDMA1: L1TXD0
TDM nibble
Peripheral Controller:
Dedicated Signal
Name
Protocol
Table 1-7. Port A Signals (Continued)
MSC8101 Technical Data
Dedicated
Direction
I/O Data
Output
Output
Output
Output
Output
Input
Input
Input
FCC1: UTOPIA Receive Data Bit 2
In the ATM UTOPIA interface supported by FCC1. The
MSC8101 inputs ATM cell octets (UTOPIA interface data) on
RXD[0–7]. RXD7 is the most significant bit. RXD0 is the least
significant bit. A cell is 53 bytes. To support Multi-PHY
configurations, RXD[0–7] is tri-stated, enabled only when
RXENB is asserted.
Module Serial Number Bit 3
MSNUM[0-4] of is the sub-block code of the current peripheral
controller using SDMA. MSNUM5 indicates which section,
transmit (0) or receive (1), is active during the transfer.
FCC1: UTOPIA RX Receive Data Bit 1
In the ATM UTOPIA interface supported by FCC1. The
MSC8101 inputs ATM cell octets (UTOPIA interface data) on
RXD[0–7]. RXD7 is the most significant bit. RXD0 is the least
significant bit. A cell is 53 bytes. To support Multi-PHY
configurations, RXD[0–7] is tri-stated, enabled only when
RXENB is asserted.
Module Serial Number Bit 4
MSNUM[0–4] of is the sub-block code of the current peripheral
controller using SDMA. MSNUM5 indicates which section,
transmit (0) or receive (1) is active during the transfer.
FCC1: UTOPIA RX Receive Data Bit 0
In the ATM UTOPIA interface supported by FCC1. The
MSC8101 inputs ATM cell octets (UTOPIA interface data) on
RXD[0–7]. RXD7 is the most significant bit. RXD0 is the least
significant bit. A cell is 53 bytes. To support Multi-PHY
configurations, RXD[0–7] is tri-stated, enabled only when
RXENB is asserted.
Module Serial Number Bit 5
MSNUM[0–4] of is the sub-block code of the current peripheral
controller using SDMA. MSNUM5 indicates which section,
transmit (0) or receive (1), is active during the transfer.
SMC2: Serial Management Transmit Data
Supported by SMC2. The SMC interface consists of SMTXD,
SMRXD, SMSYN, and a clock. Not all signals are used for all
applications. SMCs are full-duplex ports that supports three
protocols or modes: UART, transparent, or general-circuit
interface (GCI). See also PC15.
Time-Division Multiplexing A1: Layer 1 Transmit Data Bit 0
In the TDMA1 interface supported by SI1. L1TXD3 is the most
significant bit. L1TXD0 is the least significant bit in nibble
mode. TDMA1 transmits nibble data out L1TXD[0–3].
Description