MSC8101DS Motorola / Freescale Semiconductor, MSC8101DS Datasheet - Page 28

• Manufacturer Part Number: MSC8101DS
• Description: MSC8101 Network Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

1-22
Port A Signals
PA26
PA25
PA24
PA23
General-
Purpose
I/O
FCC1: RXCLAV
UTOPIA slave
FCC1: RXCLAV
UTOPIA master, or
RXCLAV0
UTOPIA master, Multi-PHY,
direct polling
FCC1: RX_ER
MII
FCC1: TXD0
UTOPIA
SDMA: MSNUM0
FCC1: TXD1
UTOPIA
SDMA: MSNUM1
FCC1: TXD2
UTOPIA
Peripheral Controller:
Dedicated Signal
Name
Protocol
Table 1-7. Port A Signals (Continued)
MSC8101 Technical Data
Dedicated
Direction
I/O Data
Output
Output
Output
Output
Output
Output
Input
Input
Input
FCC1: UTOPIA Slave Receive Cell Available
In the ATM UTOPIA interface supported by FCC1. RXCLAV is
asserted by the MSC8101 (UTOPIA slave PHY) when one
complete ATM cell is available for transfer.
FCC1: UTOPIA Master Receive Cell Available
In the ATM UTOPIA interface supported by FCC1. RXCLAV is
asserted by an external PHY when one complete ATM cell is
available for transfer.
FCC1: UTOPIA Master Receive Cell Available 0 Direct
Polling
In the ATM UTOPIA interface supported by FCC1, RXCLAV0
is asserted by an external PHY when one complete ATM cell is
available for transfer.
FCC1: Media Independent Interface Receive Error
In the MII interface and supported by FCC1. RX_ER is
asserted by an external fast Ethernet PHY. This signal
indicates a receive error, which often indicates bad wiring.
FCC1: UTOPIA Transmit Data Bit 0
In the ATM UTOPIA interface supported by FCC1. The
MSC8101 outputs ATM cell octets (UTOPIA interface data) on
TXD[0–7]. TXD7 is the most significant bit. TXD0 is the least
significant bit. When no ATM data is available, idle cells are
inserted. A cell is 53 bytes.
Module Serial Number Bit 0
MSNUM[0–4] of is the sub-block code of the current peripheral
controller using SDMA. MSNUM5 indicates which section,
transmit (0) or receive (1), is active during the transfer.
FCC1: UTOPIA Transmit Data Bit 1
In the ATM UTOPIA interface supported by FCC1. The
MSC8101 outputs ATM cell octets (UTOPIA interface data) on
TXD[0–7]. TXD7 is the most significant bit. TXD0 is the least
significant bit. When no ATM data is available, idle cells are
inserted. A cell is 53 bytes.
Module Serial Number Bit 1
MSNUM[0–4] of is the sub-block code of the current peripheral
controller using SDMA. MSNUM5 indicates which section,
transmit (0) or receive (1), is active during the transfer.
FCC1: UTOPIA Transmit Data Bit 2
TXD[0–7] is part of the ATM UTOPIA interface supported by
FCC1. The MSC8101 outputs ATM cell octets (UTOPIA
interface data) on TXD[0–7]. TXD7 is the most significant bit.
TXD0 is the least significant bit. When no ATM data is
available, idle cells are inserted. A cell is 53 bytes.
Description