MSC8101DS Motorola / Freescale Semiconductor, MSC8101DS Datasheet - Page 73

• Manufacturer Part Number: MSC8101DS
• Description: MSC8101 Network Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

Note:
Number
55
56
57
58
59
60
61
62
63
64
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. The host request is HREQ/HREQ in the single host request mode and HRRQ/HRRQ and HTRQ/HTRQ in
HCS[1–2] assertion to output data valid
HCS[1–2] hold time after data strobe deassertion
HA[0–3], HRW setup time before data strobe
assertion
HA[0–3], HRW hold time after data strobe deassertion
Delay from read data strobe deassertion to host
request assertion for “Last Data Register” read
Delay from write data strobe deassertion to host
request assertion for “Last Data Register” write
Delay from read data strobe deassertion to host
request deassertion for “Last Data Register” read
Delay from write data strobe deassertion to host
request deassertion for “Last Data Register” write
Delay from DMA HACK (OAD=0) or Read/Write data
strobe(OAD=1) deassertion to HREQ assertion.
Delay from DMA HACK (OAD=0) or Read/Write data
strobe(OAD=1) assertion to HREQ deassertion
T
In the timing diagrams below, the controls pins are drawn as active low. The pin polarity is programmable.
V
The read data strobe is HRD/HRD in the dual data strobe mode and HDS/HDS in the single data strobe
mode.
In 64-bit mode, The “last data register” is the register at address $7, which is the last location to be read or
written in data transfers. This is RX0/TX0 in the little endian mode (HBE = 0), or RX3/TX3 in the big endian
mode (HBE = 1).
This timing is applicable only if a read from the “last data register” is followed by a read from the RXL,
RXM, or RXH registers without first polling RXDF or HREQ bits, or waiting for the assertion of the
HREQ/HREQ signal.
This timing is applicable only if two consecutive reads from one of these registers are executed.
The write data strobe is HWR in the dual data strobe mode and HDS in the single data strobe mode.
The data strobe is host read (HRD/HRD) or host write (HWR/HWR) in the dual data strobe mode and host
data strobe (HDS/HDS) in the single data strobe mode.
the double host request mode. HRRQ/HRRQ is deasserted only when HOTX fifo is empty, HTRQ/HTRQ is
deasserted only if HORX fifo is full (treat as level Host Request).
C
CC
Read
Write
= 1/ DSPCLK. At 300 MHz
= 3.3 V ± 0.3 V; T
9
Table 2-16. Host Interface (HDI16) Timing
Characteristics
J
= -40°C to +100 °C, C
T
MSC8101 Technical Data
C
= 3.3 ns
3
L
= 50 pF
4, 5, 10
5,8,10
9
4, 5, 10
5,8,10
9
1, 2
(2.5
(2.5
(2.5
(2.5
(2.5
(2.5
(Continued)
Expression
T
C
T
T
T
T
T
T
—
—
—
+ 3.3
C
C
C
C
C
C
) + 3.3
) + 3.3
) + 3.3
) + 3.3
) + 3.3
) + 3.3
11.6
11.6
11.6
Min
0.0
3.3
3.3
—
—
—
—
0
HDI16 Signals
11.6
11.6
11.6
Max
6.6
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2-19