MSC8101DS Motorola / Freescale Semiconductor, MSC8101DS Datasheet - Page 15

• Manufacturer Part Number: MSC8101DS
• Description: MSC8101 Network Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

Reserved
BADDR29
IRQ2
Reserved
BADDR30
IRQ3
Reserved
BADDR31
IRQ5
BR
BG
ABB
IRQ2
Signal
Table 1-5. PowerPC System Bus, HDI16, and Interrupt Signals (Continued)
Input/Output
Input/Output
Input/Output
Data Flow
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
The primary configuration is reserved.
Burst Address 29
One of five outputs of the memory controller. These pins connect directly to memory
devices controlled by the MSC8101 memory controller.
Interrupt Request 2
One of eight external lines that can request a service routine, via the internal interrupt
controller, from the SC140 core.
The primary configuration is reserved.
Burst Address 30
One of five outputs of the memory controller. These pins connect directly to memory
devices controlled by the MSC8101 memory controller.
Interrupt Request 3
One of eight external lines that can request a service routine, via the internal interrupt
controller, from the SC140 core.
The primary configuration is reserved.
Burst Address 31
One of five outputs of the memory controller. These pins connect directly to memory
devices controlled by the MSC8101 memory controller.
Interrupt Request 5
One of eight external lines that can request a service routine, via the internal interrupt
controller, from the SC140 core.
Bus Request
An output when an external arbiter is used. The MSC8101 asserts this pin to request
ownership of the bus.
An input when an internal arbiter is used. An external master should assert this pin to
request bus ownership from the internal arbiter.
Bus Grant
An output when an internal arbiter is used. The MSC8101 asserts this pin to grant bus
ownership to an external PowerPC bus master.
An input when an external arbiter is used. The external arbiter should assert this pin to
grant bus ownership to the MSC8101.
Address Bus Busy
The MSC8101 asserts this pin for the duration of the address bus tenure. Following an
address acknowledge (AACK) signal, which terminates the address bus tenure, the
MSC8101 negates ABB for a fraction of a bus cycle and then stops driving this pin.
The MSC8101 does not assume bus ownership as long as it senses that this pin is
asserted by an external bus master.
Interrupt Request 2
One of the eight external lines that can request a service routine, via the internal
interrupt controller, from the SC140 core.
2
MSC8101 Technical Data
2
1
1
1
1
1
1
1
1
Description
1-9