MSC8101DS Motorola / Freescale Semiconductor, MSC8101DS Datasheet - Page 21

• Manufacturer Part Number: MSC8101DS
• Description: MSC8101 Network Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

TA
TEA
NMI
NMI_OUT
PSDVAL
IRQ7
INT_OUT
Note:
Signal
1.
2.
3.
See the System Interface Unit (SIU) chapter in the MCS8101 Reference Manual for details on how to
configure these pins.
When used as the bus control arbiter for the PowerPC bus, the MSC8101 can support up to three external
bus masters. Each master uses its own set of Bus Request, Bus Grant, and Data Bus Grant signals
(BR/BG/DBG, EXT_BR2/EXT_BG2/EXT_DBG2, and EXT_BR3/EXT_BG3/EXT_DBG3). Each of these
signal sets must be configured to indicate whether the external master is or is not a MSC8101 master
device. See the Bus Configuration Register (BCR) description in the System Interface Unit (SIU) chapter in
the MCS8101 Reference Manual for details on how to configure these pins. The second and third set of
pins is defined by EXT_xxx to indicate that they can only be used with external master devices. The first set
of pins (BR/BG/DBG) have a dual function. When the MSC8101 is not the bus arbiter, these signals
(BR/BG/DBG) are used by the MSC8101 to obtain master control of the bus.
See the Host Interface (HDI16) chapter in the MCS8101 Reference Manual for details on how to configure
these pins.
Table 1-5. PowerPC System Bus, HDI16, and Interrupt Signals (Continued)
Input/Output
Input/Output Transfer Error Acknowledge
Input/Output Data Valid
Data Flow
Output
Output
Input
Input
Transfer Acknowledge
Indicates that a data beat is valid on the data bus. For single beat transfers, assertion of
TA indicates the termination of the transfer. For burst transfers, TA is asserted four
times to indicate the transfer of four data beats with the last assertion indicating the
termination of the burst transfer.
Indicates a bus error. masters within the MSC8101 monitor the state of this pin. The
MSC8101 internal PowerPC bus monitor can assert this pin if it identifies a bus transfer
that is hung.
Non-Maskable Interrupt
When an external device asserts this line, the MSC8101 NMI input is asserted.
Non-Maskable Interrupt
Driven from the MSC8101 internal interrupt controller. Assertion of this output indicates
that a non-maskable interrupt, pending in the MSC8101 internal interrupt controller, is
waiting to be handled by an external host.
Indicates that a data beat is valid on the data bus. The difference between the TA pin
and PSDVAL is that the TA pin is asserted to indicate data transfer terminations while
the PSDVAL signal is asserted with each data beat movement. Thus, when TA is
asserted, PSDVAL is asserted, but when PSDVAL is asserted, TA is not necessarily
asserted. For example when the SDMA initiates a double word (2x64 bits) transfer to a
memory device that has a 32-bit port size, PSDVAL is asserted three times without TA,
and finally both pins are asserted to terminate the transfer.
Interrupt Request 7
One of eight external lines that can request a service routine, via the internal interrupt
controller, from the SC140 core.
Interrupt Output
Driven from the MSC8101 internal interrupt controller. Assertion of this output indicates
that an unmasked interrupt is pending in the MSC8101 internal interrupt controller.
MSC8101 Technical Data
1
1
Description
1-15