MSC8101DS Motorola / Freescale Semiconductor, MSC8101DS Datasheet - Page 35

• Manufacturer Part Number: MSC8101DS
• Description: MSC8101 Network Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

General-
Purpose
PB28
PB27
PB26
I/O
FCC2: RTS
HDLC serial , HDLC nibble , and
transparent
FCC2: RX_ER
MII
SCC2: RTS, TENA
SI2 TDMB2: L1TSYNC/GRANT
TDM serial
FCC2: COL
MII
SI2 TDMC2: L1TXD
TDM serial
FCC2: CRS
MII
SI2 TDMC2: L1RXD
TDM serial
Peripheral Controller:
Name
Dedicated I/O
Protocol
Table 1-8. Port B Signals (Continued)
MSC8101 Technical Data
Direction
Dedicate
Output
Output
Output
d I/O
Input
Input
Input
Input
Input
Data
FCC2: Request to Send
One of the standard modem interface signals supported by
FCC2 (RTS, CTS, and CD). RTS is asynchronous with the
data. RTS is typically used in conjunction with CD. The
MSC8101 FCC2 transmitter requests the receiver to send
data by asserting RTS low. The request is accepted when
CTS is returned low.
FCC2: Media Independent Interface Receive Error
In the MII interface supported by FCC2, RX_ER is asserted
by an external fast Ethernet PHY. This signal indicates a
receive error, which often indicates bad wiring.
SCC2: Request to Send, Transmit Enable
Typically used in conjunction with CD supported by SCC2.
The MSC8101 SCC2 transmitter requests the receiver to
send data by asserting RTS low. The request is accepted
when CTS is returned low. TENA is the signal used in
Ethernet mode.
Time-Division Multiplexing B2: Layer 1 Transmit
Synchronization
In the TDMB2 interface supported by SI2, this is the
synchronizing signal for the transmit channel. If Grant Mode
is enabled this bit is sampled as the Grant bit for IDL mode
access for the D channel. See the Serial Interface with
Time-Slot Assigner chapter in the MSC8101 Technical
Reference manual.
FCC2: Media Independent Interface Collision Detect
In the MII interface supported by FCC2. COL is asserted by
an external fast Ethernet PHY.
Time-Division Multiplexing C2: Layer 1 Transmit Data
In the TDMC2 interface supported by SI2. L1TXD supports
serial mode. TDMC2 transmits serial data out of L1TXD.
FCC2: Media Independent Interface Carrier Sense Input
In the MII interface, CRS is asserted by an external fast
Ethernet PHY. This signal indicates activity on the cable.
Time-Division Multiplexing C2: Layer 1 Receive Data
In the TDMC2 interface supported by SI2. L1RXD supports
serial mode. TDMC2 receives serial data from L1RXD.
Description
Port B Signals
1-29