MSC8101DS Motorola / Freescale Semiconductor, MSC8101DS Datasheet - Page 54

• Manufacturer Part Number: MSC8101DS
• Description: MSC8101 Network Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

1.7
The MSC8101 supports the standard set of Test Access Port (TAP) signals defined by IEEE 1149.1 Standard
Test Access Port and Boundary-Scan Architecture specification and described in Table 1-11.
1.8
1-48
Port D Signals
TCK
TDI
TDO
TMS
TRST
TEST
THERM[1–2]
SPARE1, 5
Signal Name
Signal Name
JTAG Test Access Port Signals
Reserved Signals
Type
Input
—
—
Output
Type
Input
Input
Input
Input
Table 1-11. JTAG Test Access Port Signals
Test
Used for manufacturing testing. You must connect this input to GND.
Leave disconnected.
Spare Pins
Leave disconnected for backward compatibility with future revisions of this device.
Test Clock—A test clock signal for synchronizing JTAG test logic.
Test Data Input—A test data serial signal for test instructions and data. TDI is
sampled on the rising edge of TCK and has an internal pull-up resistor.
Test Data Output—A test data serial signal for test instructions and data. TDO
can be tri-stated. The signal is actively driven in the shift-IR and shift-DR
controller states and changes on the falling edge of TCK.
Test Mode Select—Sequences the test controller’s state machine, is sampled
on the rising edge of TCK, and has an internal pull-up resistor.
Test Reset—Asynchronously initializes the test controller, has an internal
pull-up resistor, and must be asserted after power up.
Table 1-12. Reserved Signals
MSC8101 Technical Data
Signal Description
Signal Description