MSC8101DS Motorola / Freescale Semiconductor, MSC8101DS Datasheet - Page 78

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MSC8101DS

Manufacturer Part Number
MSC8101DS
Description
MSC8101 Network Digital Signal Processor
Manufacturer
Motorola / Freescale Semiconductor
Datasheet
Note:
2-24
CPM Timings
The timing values listed are preliminary and refer to minimum system timing requirements. Actual
implementation requires conformance to the specific protocol requirements. Refer to Section
Chapter 1, Signal/Connection Descriptions to identify the specific input and output signals
associated with the referenced internal controllers and supported communication protocols. For
example, FCC1 supports ATM/Utopia operation in slave mode, multi-PHY master direct polling
mode, and multi-PHY master multiplexed polling mode and each of these modes supports its own
set of signals; the direction (input or output) of some of the shared signal names depends on the
selected mode.
PIO/TIMER/DMA outputs
Serial input clock
PIO/TIMER/DMA inputs
SCC/SMCSPI/I
Figure 2-14. SCC/SMC/SPI/I
TDM outputs
SCC/SMC/SPI/I
TDM inputs
Figure 2-16. PIO, Timer, and DMA Signal Diagram
Serial input clock
Figure 2-15. TDM Signal Diagram
CLKIN
2
C outputs
2
MSC8101 Technical Data
C inputs
22
20
18b
2
C External Clock Diagram
21
40
23
38b
19b
42

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