MSC8101DS Motorola / Freescale Semiconductor, MSC8101DS Datasheet - Page 29

• Manufacturer Part Number: MSC8101DS
• Description: MSC8101 Network Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

PA22
PA21
PA20
PA19
General-
Purpose
I/O
FCC1: TXD3
UTOPIA
FCC1: TXD4
UTOPIA
FCC1: TXD3
MII and HDLC nibble
FCC1: TXD5
UTOPIA
FCC1: TXD2
MII and HDLC nibble
FCC1: TXD6
UTOPIA
FCC1: TXD1
MII and HDLC nibble
Peripheral Controller:
Name
Dedicated Signal
Protocol
Table 1-7. Port A Signals (Continued)
MSC8101 Technical Data
Dedicated
Direction
I/O Data
Output
Output
Output
Output
Output
Output
Output
FCC1: UTOPIA Transmit Data Bit 3
TXD[0–7] is part of the ATM UTOPIA interface supported by
FCC1. The MSC8101 outputs ATM cell octets (UTOPIA
interface data) on TXD[0–7]. TXD7 is the most significant bit.
TXD0 is the least significant bit. When no ATM data is
available, idle cells are inserted. A cell is 53 bytes.
FCC1: UTOPIA Transmit Data Bit 4
TXD[0–7] is part of the ATM UTOPIA interface supported by
FCC1. The MSC8101 outputs ATM cell octets (UTOPIA
interface data) on TXD[0–7]. TXD7 is the most significant bit.
TXD0 is the least significant bit. When no ATM data is
available, idle cells are inserted. A cell is 53 bytes.
FCC1: MII and HDLC Nibble Transmit Data Bit 3
TXD[3–0] supports MII and HDLC nibble modes in FCC1.
TXD3 is the most significant bit. TXD0 is the least significant
bit.
FCC1: UTOPIA Transmit Data Bit 5
TXD[0–7] is part of the ATM UTOPIA interface supported by
FCC1. The MSC8101 outputs ATM cell octets (UTOPIA
interface data) on TXD[0–7]. TXD7 is the most significant bit.
TXD0 is the least significant bit. When no ATM data is
available, idle cells are inserted. A cell is 53 bytes.
FCC1: MII and HDLC Nibble Transmit Data Bit 2
TXD[3–0] is supported by MII and HDLC nibble modes in
FCC1. TXD3 is the most significant bit. TXD0 is the least
significant bit.
FCC1: UTOPIA Transmit Data Bit 6
TXD[0–7] is part of the ATM UTOPIA interface supported by
FCC1. The MSC8101 outputs ATM cell octets (UTOPIA
interface data) on TXD[0–7]. TXD7 is the most significant bit.
TXD0 is the least significant bit. When no ATM data is
available, idle cells are inserted. A cell is 53 bytes.
FCC1: MII and HDLC Nibble Transmit Data Bit 1
TXD[3–0] is supported by MII and HDLC transparent nibble
modes in FCC1. TXD3 is the most significant bit. TXD0 is the
least significant bit.
Description
Port A Signals
1-23