MSC8101DS Motorola / Freescale Semiconductor, MSC8101DS Datasheet - Page 68

• Manufacturer Part Number: MSC8101DS
• Description: MSC8101 Network Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

2-14
Reset Timing
Output (I/O)
Output (I/O)
PORESET
PORESET
HRESET
SRESET
Internal
Input
asserted for
CLKIN.
min 16
1
In reset configuration
mode: reset configuration
sequence occurs in this
period.
RSTCONF is sampled for
master/slave determination
Figure 2-3. Hardware Reset Configuration Timing
2
MSC8101 Technical Data
PLL locked
800 reference clocks
(CLKIN/PDF). DLL locks
3073 bus clocks after
PLL is locked.
When DLL is disabled,
reset period is shortened
by 3073 bus clocks.
PLL locks after
MODCK[1–3] are
sampled. MODCK_H
bits are ready for PLL.
3
DLL locked
4
HRESET /SRESET are
extended for 512/515 bus
clocks, respectively, from
PLL and DLL Lock time.
5
6