HFC-SP Cologne Chip AG, HFC-SP Datasheet - Page 11

• Manufacturer Part Number: HFC-SP
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

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1)
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Pin No.
open drain, external pull up resistor required
13
15
16
17
18
21
22
23
24
25
26
27
28
10
11
12
14
*
If DMA acknowledge signals /DMAAK0 and /DMAAK1 are active, the function of the
read/write enables is inverted. This means a read command on the controller databus
writes the AUX-Channel register and a write command reads the register. The address on
the address bus (SA0-SA7) is ignored.
important!
SA8
IOCHRDY
SA5
SA6
SA7
/DMAAK0
SA9
/DMAAK1
/AEN
/CE1
/CS
/WAIT
/WAIT
/IOR
/IORD
/DS
/IOW
/IOWR
R/W
BD0
BD1
BD2
BD3
BD4
BD5
BD6
BD7
Pin Name
Output
Input
O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
1)
1)
1)
all
all
all
1,5,6
2,3,4
1,5,6
2,3,4
1,5
6
2,3,4
1,5
2,3,4
6
1,3,4,5
6
2
1,3,4,5
6
2
all
all
all
all
all
all
all
all
Mode
Function
Address bit 5
Address bit 6
(SA6 must be connected to GND in processor mode)
Address bit 7
Address bit 8
DMA acknowledge channel 0
Direct access to GCI/IOM2 bus AUX1 channel data
register (low active)
address bit 9
DMA acknowledge channel 1
direct access on GCI/IOM2 bus AUX2 channel
dataregister (low active)
PC bus address enable
Card enable (low active)
chipselect low active
I/O channel ready
low active wait signal for external processor
Extended bus cycle (low active)
I/O read enable
I/O read (low active)
I/O data strobe
I/O write enable
I/O write (low active)
Read/Write select (WR='0')
Databus bit 0 (LSB)
Databus bit 7 (MSB)
Databus bit 1
Databus bit 2
Databus bit 3
Databus bit 4
Databus bit 5
Databus bit 6
Cologne
Chip
!! _V (#