HFC-SP Cologne Chip AG, HFC-SP Datasheet - Page 24

• Manufacturer Part Number: HFC-SP
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

863 C@
3.4
Processor mode is selected by MODE = NC and IIOSEL0..3=0.
In the microprocessor mode the HFC-SP uses 256 I/O addresses (SA0 - SA7).
*)
All registers are directly accessable by their I/O address (see register description).
Except in mode 4 ALE is assumed to be stable after a RESET.
"$ _V (#
1-pulse latches I/O address.
X = don't care
*
For write accesses to the HFC-SP the data lines must be stable and valid before /IOW or /DS get
low (see also: Timing diagram 1 on page 59). With Intel compatible processors it may be
neccessary to delay the /IOW or /DS signals.
/IOR
/DS
X
important!
1
0
0
0
1
0
1
Processor mode
/IOW
R/W
X
1
1
0
1
0
1
0
/CS
X
1
0
0
0
0
0
0
ALE
0
0
X
X
1
1
0
0
*)
*)
Operation
write data
write data
write data
no access
no access
read data
read data
read data
Mode
all
all
2
3
2
3
4
4
:Q^eQbi " !
Cologne
Chip