HFC-SP Cologne Chip AG, HFC-SP Datasheet - Page 39

• Manufacturer Part Number: HFC-SP
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

863 C@
3.9.1.6 FIFO reset
All counters Z1, Z2, F1 and F2 of all FIFOs are initialized to all 1s after a RESET.
Then the result is Z1 = Z2 = 1FFFh and F1 = F2 = 1Fh for the B-channels
and Z1 = Z2 = 1FFh and F1 = F2 = 1Fh for the D-channel.
Please mask bit 4 of D-channel from counter F1, F2.
The same initialisation is done if the bit 3 in the CIRM register is set (soft reset).
Individual FIFOs can be reset by bit 7 of CIRM register.
3.9.2 Transparent mode of HFC-SP
You can switch off HDLC operation for each B-channel independently. There is one bit for each B-
channel in the CTMT control register. If this bit is set data in the FIFO is sent directly to the S/T or
GCI/IOM2 bus interface and data from the S/T or GCI/IOM2 bus interface is sent directly to the FIFO.
Be sure to switch into transparent mode only if F1=F2. Being in transparent mode the Fx counters remain
unchanged. Z1 and Z2 are the input and output pointers respectively. Because F1=F2 both Z-counters are
always accessable and have valid data.
Because always one Z-counter is changed by the HFC-SP and only 8 bits of a counter can be read at a
time the counter should be read twice to check for a counter incrementation between low and high byte
accesses.
If a send FIFO channel changes to FIFO empty condition no CRC is generated and the last data byte
written into the FIFO is repeated until there is new data.
In receive channels there is no check on flags or correct CRCs and no status byte is added.
The byte bounderies are not arbitrary like in HDLC mode where byte synchronisation is achieved with
HDLC-flags. The data is just the same as it comes from the S/T or GCI/IOM2 bus interface or is sent to
this.
Send and receive transparent data can be handled in two ways. The usual way is tranporting B-channel
data with the LSB first as it is usual in HDLC mode. The second way is sending the bytes in reverse bit
order as it is usual for PWM data. So the first bit is the MSB. The bit order can be reversed by setting bit
7 of the FIF_SEL register when the FIFO is selected.
:Q^eQbi " !
Cologne
Chip
#) _V (#