HFC-SP Cologne Chip AG, HFC-SP Datasheet - Page 6

• Manufacturer Part Number: HFC-SP
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

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Features
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The HFC-SP is an ISDN S/T HDLC basic rate controller for so called „passive“ ISDN PC cards with
integrated S/T interface and PCM30 highway interface. It only needs an external SRAM to form a high
performance ISDN PC card. Most problems with passive ISDN PC cards as small FIFOs and massive
interrupt load for the host CPU are overcome by the HFC-SP. So we call ISDN cards with the HFC-SP
„semi-active“.
Additionally the HFC-SP can be used as a microprocessor peripheral in non-PC applications.
The ultra deep FIFOs of the HFC-SP are realized with an external SRAM. Also an industrial standard
serial interface for telecom peripheral ICs is implemented. Codecs are normally connected to this
interface.
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One chip ISDN-S-controller with B- and D-channel HDLC support
Independent Read and Write HDLC-Channels for 2 ISDN B-channels and one ISDN D-channel
B1 and B2 transparent mode independently selectable
FIFO-size: 4x 7.5 KByte (B-channel) and 2x 512 Byte (D-channel)
max. 31 HDLC frames (B-channel) and 15 HDLC frames (D-channel) per channel and direction
in FIFO
56 kbit/s restricted mode for U.S. ISDN lines selectable
full I.430 ITU S/T ISDN support in TE and NT mode for 3.3V and 5V supply
B1+B2 HDLC mode
PCM30 interface configurable to interface MITEL ST
GCI
direct 8 bit ISA-PC bus interface with buffers for ISA-databus
integrated ISA Plug and Play (Windows 95 Spec.)
only 2 I/O addresses used on ISA-PC bus
one of 7 interrupt channels on ISA-PC bus selectable by software
integrated PCMCIA interface
microprocessor interface compatible to Motorala bus and Siemens/Intel bus
simple access to PCM30 interface for tone synthetisation
Timer with interrupt and watchdog capability in processor mode
3-5V supply voltage
rectangular QFP 100 case
General description
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for interface to U-chip or external codecs
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bus (MVIP
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), Siemens IOM2
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