HFC-SP Cologne Chip AG, HFC-SP Datasheet - Page 48

• Manufacturer Part Number: HFC-SP
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

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Name
MST_MODE
*
Auxiliary channel handling
If the data registers AUX1_D and AUX2_D are not overwritten, the transmisson slots AUX1_SSL
and AUX2_SSL mirror the data received in AUX1_RSL and AUX2_RSL slots. This is useful for
an internal connection between two CODECs. This mirroring is disabled by setting bit 1 in
MST_EMOD register.
In ISA, ISA-PnP and PCMCIA mode: To use the AUX1 channel the address pin SA8 must be '1'
at every access to the HFC-SP. To use the AUX2 channel the address pin SA9 must be '1' at every
access to the HFC-SP. The PnP information must be set accordingly.
The pulse shape and polarity of the codec signals F1_A and F1_B is the same as the pulseshape of the
F0IO signal. The polatity of C2O can be changed by bit 1.
RESET sets register MST_MODE to all '0's.
note!
Addr.
2Eh
Bits
5, 4
7, 6
0
1
2
3
r/w Function
w
w
w
w
w
w
GCI/IOM2 bus mode
'0' slave (reset default) (C4IO and F0IO are inputs)
'1' master (C4IO and F0IO are outputs)
polarity of C4- and C2O-clock
'0' F0IO is sampled on negative clock transition
'1' F0IO is sampled on positive clock transition
polarity of F0-signal
'0' F0 positive pulse
'1' F0 negative pulse
duration of F0-signal
'0' F0 active for one C4-clock (244ns) (reset default)
'1' F0 active for two C4-clocks (488ns)
time slot for codec-A signal F1_A
'00' B1 receive slot
'01' B2 receive slot
'10' AUX1 receive slot
'11' signal C2O
time slot for codec-B signal F1_B
'00' B1 receive slot
'01' B2 receive slot
'10' AUX1 receive slot
'11' AUX2 receive slot
pin F1_A (C2O is 2048 kHz clock)
:Q^eQbi " !
Cologne
Chip