HFC-SP Cologne Chip AG, HFC-SP Datasheet - Page 59

• Manufacturer Part Number: HFC-SP
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

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6
6.1
Timing diagram 1: ISA-PC bus or microprocessor access
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SYMBOL
t
t
t
t
t
t
t
t
t
t
t
RDD
RDDH
SA
SAH
RD
WR
WRDSU
WRDH
RDY
RDYH
BUSRD
Timing characteristics
ISA-PC bus or processor access
/IOR Low to Read Data Out Time
/IOR High to Data Buffer Turn Off Time
Address to /IOR or /IOW Low Setup Time
Address Hold Time after /IOR or /IOW High
Read Time
Write Time
Write Data Setup Time to /IOW Low
Write Data Hold Time from /IOW High
Delay Time from /IOR or /IOW Low to IOCHRDY Low
Delay Time from /IOR Low or /IOW High to IOCHRDY High
Delay Time from /IOR Low to BUSDIR Low
CHARACTERISTICS
MIN.
20ns
20ns
50ns
50ns
30ns
10ns
3ns
2ns
3ns
3ns
3ns
Cologne
Chip
MAX.
25ns
15ns
30ns
30ns
25ns
%) _V (#
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