HFC-SP Cologne Chip AG, HFC-SP Datasheet - Page 5

• Manufacturer Part Number: HFC-SP
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

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12
12.1
12.2
Figures
Figure 1: HFC-SP block diagram.................................................................................................................. 7
Figure 2: Pin Connection ............................................................................................................................ 10
Figure 3: FIFO Organisation (shown for B-channel, similar for D-channel) ............................................. 35
Figure 4: FIFO Data Organisation .............................................................................................................. 37
Figure 5: Connecting an external device to the HFC-SP............................................................................ 41
Figure 6: Function of the CONNECT register bits..................................................................................... 50
Figure 7: GCI/IOM2 bus clock and data alignment.................................................................................... 61
Figure 8: External receiver circuitry........................................................................................................... 66
Figure 9: External transmitter circuitry ...................................................................................................... 67
Figure 10: Oscillator Circuitry.................................................................................................................... 70
Figure 11: EEPROM circuitry .................................................................................................................... 70
Figure 12: Frame structure at reference point S and T ............................................................................... 73
Figure 13: Single channel GCI format........................................................................................................ 74
Figure 14: Clock synchronisation in NT-mode .......................................................................................... 75
Figure 15: Clock synchronisation in TE-mode........................................................................................... 76
Figure 16: HFC-SP package dimensions .................................................................................................... 77
Tables
Table 1: Mode selection................................................................................................................................ 8
Table 2: Selected I/O address after reset .................................................................................................... 17
Table 3: DMA access in processor mode ................................................................................................... 25
Table 4: SRAM and FIFO size ................................................................................................................... 40
Table 5: S/T module part numbers and manufacturer ................................................................................ 69
Table 6: Activation/deactivation layer 1 for finite state matrix for NT ..................................................... 71
Table 7: Activation/deactivation layer 1 for finite state matrix for TE...................................................... 72
Timing Diagrams
Timing diagram 1: ISA-PC bus or microprocessor access ......................................................................... 59
Timing diagram 2: SRAM access ............................................................................................................... 60
Timing diagram 3: GCI/IOM2 timing......................................................................................................... 62
Timing diagram 4: EEPROM access .......................................................................................................... 64
Timing diagram 5: Access to an external device ........................................................................................ 65
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Sample circuitries with HFC-SP..................................................................................................... 78
ISDN ISA PnP PC card ............................................................................................................. 78
ISDN PCMCIA card.................................................................................................................. 81
Cologne
Chip
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