HFC-SP Cologne Chip AG, HFC-SP Datasheet - Page 26

• Manufacturer Part Number: HFC-SP
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

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3.5
3.5.1 Internal HFC-SP register selection
The HFC-SP occupies two consecutive addresses in the I/O map. The base I/O address must be 2 byte
aligned so the lower of both addresses is the one with SA0 = 0 and the higher address is the one with
SA0 = 1. The lines SA1 to SA11 are don't care. The registers of the HFC-SP are selected by writing the
registers' address to the higher I/O address (SA0=1). Registers are read/written by reading/writing the
base I/O address (SA0=0).
3.5.2 Attribute memory
After hardware reset the card's information structure (CIS) is copied from the EEPROM to even
numbered addresses of the SRAM starting with 0000h (288 byte are occupied for the CIS). To avoid
accesses in this phase the /WAIT signal is active.
3.5.3 PCMCIA registers
Configuration Option Register (COR):
The fields are as follows:
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SRESET
LevIREQ
Configuration Index
SRESET
D7
PCMCIA mode
LevIREQ
D6
1
SRESET card. Setting this bit to one places the card in the reset state. This bit
must be cleared to zero by the user.
This bit is not implemented and returns always 1 when read to indicate usage of
level mode interrupts.
Configuration Index.
Bit 0 must be set to 1 to enable I/O accesses to the HFC-SP.
Bit 5 must be set to 1 to write data to the EEPROM.
D5
D4
Register address: 400h in Configuration Memory
Configuration Index
D3
D2
D1
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Cologne
Chip
D0