HFC-SP Cologne Chip AG, HFC-SP Datasheet - Page 9

• Manufacturer Part Number: HFC-SP
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

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1.2.3 Processor interface modes
The processor modes are selected by IIOSEL3-0 = '0000' and MODE left open.
In all processor modes line SA6 must be connected to GND.
Mode 2:
Mode 3:
Mode 4:
The lines SA0-SA7 (except SA6) are used for direct addressing the internal registers of the HFC-SP (see
also 3.4).
1.2.4 PCMCIA mode
Mode 6:
In mode 6 the HFC-SP is addressed by two successive port addresses. The port address is selected by the
lines SA0 - SA11.
The address with SA0='1' is for register selection and the address with SA0='0' is used for data read/write
(see also: 3.5).
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Motorola bus with control signals /CS, R/W, /DS is selected by setting ALE to VDD.
Siemens/Intel bus with seperated address bus and databus and control signals /CS, /WR,
/RD is selected by setting ALE to GND.
Intel bus with multiplexed address and databus with control signals /CS, /WR, /RD,
ALE.
ALE latches the address. The address lines SA0-SA7 must be connected to the data lines
BD0-BD7 (except SA6 which must be connected to GND).
PCMCIA mode is selected by: ALE = GND and MODE = VDD
Cologne
Chip
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