HFC-SP Cologne Chip AG, HFC-SP Datasheet - Page 49

• Manufacturer Part Number: HFC-SP
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

863 C@
RESET sets register MST_EMOD to all '0's.
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Name
MST_EMOD
C/I
TRxR
Addr.
2Dh
02h
03h
Bits
5..3
3..0
7..4
5..2
0
1
2
6
7
0
1
6
7
r/w Function
r/w on read: indication
w
w
w
w
w
w
r
r
r
r
r
'0' C4IO clock is adjusted in the 31th time slot twice for one
'1' C4IO clock is adjusted in the 31th time slot once for one
enable/disable AUX channel mirroring
'0' mirror AUX receive to AUX transmit (reset default)
'1' disable AUX channel data mirroring
unused
select D-channel data flow (see also: CONNECT register)
bit 3: '0'
bit 4: '0'
bit 5: '0'
unused
enable GCI/IOM2 write slots
'0' disable GCI/IOM2 write slots; slot #2 and slot #3 may be
'1' enables slot #2 and slot #3 as master, D- and C/I-channel
on write: command
'1' Monitor transmitter ready
Writing on MON2_D starts transmisssion and resets this bit.
STIO2 in
STIO1 in
slow down C4IO clock adjustment (see Figure 15)
unused
reserved
reserved
used for normal data
half clock cycle (reset default)
half clock cycle
'1'
'1'
'1'
destination
D-HFC
D-HFC
D-S/T
D-S/T
D-GCI/IOM2
D-GCI/IOM2
source
D-S/T
D-GCI/IOM2
D-HFC
D-GCI/IOM2
D-HFC
D-S/T
Cologne
Chip
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