HFC-SP Cologne Chip AG, HFC-SP Datasheet - Page 42

• Manufacturer Part Number: HFC-SP
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

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3.13
For electrical tests of layer 1 it is useful to create a S/T test loop for the B1/B2 channel. The test loop
described here transmits the data that has been received on the B1 or B2 channel to the same channel on
the S/T interface. To configure this loop the following must be done:
- write 0Fh to register CLKDEL (37h)
- write 43h to register SCTRL (31h)
- write 00h to register STATES (30h)
- write 03h to register SCTRL_R (33h)
- write 36h to register CONNECT (2Fh)
- write 80h to register B1_SSL (20h)
- write C0h to register B1_RSL (24h)
- write 81h to register B2_SSL (21h)
- write C1h to register B2_RSL (25h)
- write 01h to register MST_MODE (2Eh)
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Configuring test loops
// Adjust the phase offset between receive and
// transmit direction (value depends on the external
// circuitry).
// 03h is to enable B1, B2 at the S/T interface for
// transmission
// 40h is for TX_LO setup (capacitive line mode)
// Release S/T state machine for activation over the
// S/T interface by incoming INFO 2 or INFO 4.
// Configure S/T B1 and B2 channel to normal
// receive operation.
// Configure CONNECT register for B1/B2 channel
// test loop.
// Enable transmit channel for GCI/IOM2 bus, pin
// STIO1 is used as output, use time slot #0.
// Enable receive channel for GCI/IOM2 bus, pin
// STIO1 is used as input, use time slot #0.
// Enable transmit channel for GCI/IOM2 bus, pin
// STIO1 is used as output, use transmission slot #1.
// Enable receive channel for GCI/IOM2 bus, pin
// STIO1 is used as input, use time slot #1.
// Configure HFC-SP as GCI/IOM2 bus master.
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