HFC-SP Cologne Chip AG, HFC-SP Datasheet - Page 38

• Manufacturer Part Number: HFC-SP
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

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After reading a frame via the host bus interface F2 must be incremented. If the frame counter F2 is
incremented also the Z-counters may change because Z1 and Z2 are functions of F1 and F2. So there are
Z1(F1), Z2(F1), Z1(F2) and Z2(F2) (see Figure 3).
Z1(F1) is used for the frame which is just received from the S/T device side of the HFC. Z2(F2) is used
for the frame which is just beeing transmitted to the host bus interface. Z1(F2) is the end of frame pointer
of the current output frame.
To calculate the length of the current receive frame the software has to evaluate Z1-Z2+1. When Z2
reaches Z1 the complete frame has been read.
In the receive channels F2 must be incremented from the host interface side after the software detects an
end of receive frame (Z1=Z2) and F1 F2. Then the current value of Z2 is stored, F2 is incremented and
Z2 is copied as start address of the next frame. If Z1 = Z2 and F1 = F2 the FIFO is totally empty. Z1(F1)
can not be accessed.
3.9.1.5 FIFO full condition in receive channels
Because the ISDN-B-channels and the ISDN-D-channels have no hardware based flow control there is no
possibility to stop input data if a receive FIFO is full.
So there is no FIFO full condition implemented in the HFC-SP. The HFC-SP assumes that the FIFOs are
so deep that the host processor hard- and software is able to avoid any overflow of the receive FIFOs.
Overflow conditions are again more than 31 input frames (15 frames for D-channel) or a real overflow of
the FIFO because of excessive data.
Because HDLC procedures only know a window size of 7 frames no more than 7 frames are sent without
software intervention. Due to the great size of the FIFOs of the HFC-SP it is easy to poll the HFC-SP
even in large time intervalls without having to fear a FIFO overflow condition.
However to avoid any undetected FIFO overflows the software driver should check the number of frames
in the FIFO which is F1-F2. An overflow exists if the number (F1-F2) is less than the number in the last
reading even if there was no reading of a frame in between.
After a detected FIFO overflow condition this FIFO must be reset by setting the FIFO reset bit in the
CIRM register.
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*
Before reading a FIFO a change FIFO operation (see also: FIF_SEL register) must be done even if
the desired FIFO is already selected. The change FIFO operation is required to update the internal
buffer of the HFC-SP. Otherwise the first byte of the FIFO will be taken from the internal buffer
and may be invalid.
important!
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Cologne
Chip