HFC-SP Cologne Chip AG, HFC-SP Datasheet - Page 73

• Manufacturer Part Number: HFC-SP
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

863 C@
9
9.1
The frame structures on the S/T interface are different for each direction of transmission. Both structures
are illustrated in Figure 12.
Figure 12: Frame structure at reference point S and T
F
L
D
E
F
M
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A
*
Lines demarcate those parts of the frame that are independently d.c.-balanced.
The F
enabled (see SCTRL register).
The nominal 2-bit offset is as seen from the TE. The offset can be adjusted with the CLKDEL
register in TE mode. The corresponding offset at the NT may be greater due to delay in the
interface cable and varies by configuration.
HDLC-B-channel data start with the LSB, PCM-B-channel data start with the MSB.
note!
Binary organisation of the frames
S/T frame structure
Framing bit
D.C. balancing bit
D-channel bit
D-echo-channel bit
Auxiliary framing bit
Multiframing bit
A
bit in the direction TE to NT is used as Q bit in every fifth frame if S/Q bit transmission is
N
B1
B2
S
A
Bit set to a binary value N =
Bit within B-channel 1
S-channel bit
Bit within B-channel 2
Bit used for activation
F
A
(NT to TE)
Cologne
Chip
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